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The following commit makes the Tegra APB DMA engine fail to initialize
correctly: 0cf6230af909a86f81907455eca2a5c9b8f68fe6
ARM: tegra: Move tegra_common_init to tegra_init_early
The reason is that tegra_init_early_ calls tegra_dma_init which calls
request_threaded_irq, which fails since the IRQ hasn't yet been marked
valid; that only happens in tegra_init_irq, which gets called after
tegra_init_early.
This used to work OK, since tegra_init_early was tegra_common_init, which
got called after tegra_init_irq, basically from the beginning of
tegra_harmony_init.
Solve this by converting tegra_dma_init to a postcore_initcall. This makes
it execute late enough that IRQs are marked valid, and avoids having to
add it back to every machine's init function.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
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Enable the cpu, emc (memory controller) and csite (debug and
trace controller) clocks during init to prevent them from
being disabled by the bootloader clock disabling code.
Signed-off-by: Colin Cross <ccross@android.com>
Acked-by: Olof Johansson <olof@lixom.net>
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Move tegra_common_init to tegra_init_early, and set it
as the init_early entry in the machine struct.
Initializes the clocks earlier so that timers can enable
their clocks.
Also reorders the members in the Harmony and Trimslice
boards' machine structs to match the order they are
called in.
Signed-off-by: Colin Cross <ccross@android.com>
Acked-by: Olof Johansson <olof@lixom.net>
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This seems to be a regression in 2.6.37.
We cannot use writel() here since the resulting wmb() calls l2x0_cache_sync()
which uses a spinlock and L1 cache may be off at this point.
http://lists.infradead.org/pipermail/linux-arm-kernel/2011-February/041909.html
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Colin Cross <ccross@android.com>
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Signed-off-by: Colin Cross <ccross@android.com>
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Signed-off-by: Colin Cross <ccross@android.com>
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The APB DMA block handles DMA transfers to and from some peripherals
in the Tegra SOC. It reads from sequential addresses on the memory
bus, and writes repeatedly to the same address on the APB bus.
Two transfer modes are supported, oneshot for transferring a known
size to or from a peripheral, and continuous for streaming data.
In continuous mode, a callback occurs when the buffer is half full
to allow the existing data to be handled and a new request queued.x
v2 changes:
dma API no longer uses PTR_ERR
Signed-off-by: Erik Gilling <konkers@android.com>
Signed-off-by: Colin Cross <ccross@android.com>
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Renames clocks in the clock init table to match the datasheet names
Signed-off-by: Colin Cross <ccross@android.com>
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The Tegra SOC contains fuses to identify the CPU type and
bin, and a unique id. The CPU info is required to determine
the correct voltages for each cpu and core frequency.
Signed-off-by: Colin Cross <ccross@android.com>
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v2: fixes from Russell King:
- include linux/io.h instead of asm/io.h
- fix whitespace in Kconfig
- Use spin_lock_init to initialize lock
- Return -ENOSYS instead of BUG for unimplemented clock ops
- Use proper return values in tegra2 clock ops
additional changes:
- Rename some clocks to match dev_ids
- add rate propagation
- add debugfs entries
- add support for clock listed in clk_lookup under multiple dev_ids
v3:
- Replace per-clock locking with global clock lock
- Autodetect clock state on init
- Let clock dividers pick next lower possible frequency
- Add support for clock init tables
- Minor bug fixes
- Fix checkpatch issues
Signed-off-by: Colin Cross <ccross@android.com>
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v2: Fixes from Mike Rapoport
- remove unused header files (mach/dma.h and mach/nand.h)
- remove tegra 1 references from Makefile.boot
v2: fixes from Russell King
- remove mach/io.h include from mach/iomap.h
- fix whitespace in Kconfig
v2: from Colin Cross
- fix invalid immediate in debug-macro.S
v3:
- allow selection of multiple boards
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Erik Gilling <konkers@android.com>
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