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* Fix common misspellingsLucas De Marchi2011-03-311-1/+1
| | | | | | Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
* m68knommu: external interrupt support to ColdFire intc-2 controllerGreg Ungerer2011-03-151-0/+3
| | | | | | | | | | The EDGE Port module of some ColdFire parts using the intc-2 interrupt controller provides support for 7 external interrupts. These interrupts go off-chip (that is they are not for internal peripherals). They need some special handling and have some extra setup registers. Add code to support them. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: remove ColdFire CLOCK_DIV config optionGreg Ungerer2011-03-151-0/+1
| | | | | | | | | | The reality is that you do not need the abiltity to configure the clock divider for ColdFire CPUs. It is a fixed ratio on any given ColdFire family member. It is not the same for all ColdFire parts, but it is always the same in a model range. So hard define the divider for each supported ColdFire CPU type and remove the Kconfig option. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: clean up use of MBAR for DRAM registers on ColdFire startGreg Ungerer2011-03-151-5/+5
| | | | | | | | | | | | In some of the RAM size autodetection code on ColdFire CPU startup we reference DRAM registers relative to the MBAR register. Not all of the supported ColdFire CPUs have an MBAR, and currently this works because we fake an MBAR address on those registers. In an effort to clean this up, and eventually remove the fake MBAR setting make the DRAM register address definitions actually contain the MBAR (or IPSBAR as appropriate) value as required. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: move ColdFire DMA register addresses to per-cpu headersGreg Ungerer2011-03-151-0/+9
| | | | | | | | | | | The base addresses of the ColdFire DMA unit registers belong with all the other address definitions in the per-cpu headers. The current definitions assume they are relative to an MBAR register. Not all ColdFire CPUs have an MBAR register. A clean address define can only be acheived in the per-cpu headers along with all the other chips peripheral base addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: remove use of MBAR value for ColdFire 523x peripheral addressingGreg Ungerer2011-03-151-3/+12
| | | | | | | | The ColdFire 523x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: move ColdFire PIT timer base addressesGreg Ungerer2011-03-151-1/+8
| | | | | | | | | | | | The PIT hardware timer module used in some ColdFire CPU's is not always addressed relative to an IPSBAR register. Parts like the ColdFire 5207 and 5208 have fixed peripheral addresses. So lets not define the register addresses of the PIT relative to an IPSBAR definition. Move the base address definitions into the per-part headers. This is a lot more consistent since all the other peripheral base addresses are defined in the per-part header files already. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: remove kludge seting of MCF_IPSBAR for ColdFire 54xxGreg Ungerer2011-03-151-2/+3
| | | | | | | | | | | | | | | The ColdFire 54xx family shares the same interrupt controller used on the 523x, 527x and 528x ColdFire parts, but it isn't offset relative to the IPSBAR register. The 54xx doesn't have an IPSBAR register. By including the base address of the peripheral registers in the register definitions (MCFICM_INTC0 and MCFICM_INTC1 in this case) we can avoid having to define a fake IPSBAR for the 54xx. And this makes the register address definitions of these more consistent, the majority of the other register address defines include the peripheral base address already. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: create bit definitions for the version 2 ColdFire cache controllerGreg Ungerer2011-01-051-0/+2
| | | | | | | | The version 2 ColdFire CPU based cores all contain a similar cache controller unit. Create a set of bit flag definitions for the supporting registers. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: move UART addressing to part specific includesGreg Ungerer2011-01-051-0/+7
| | | | | | | | | | | | | The ColdFire UART base addresses varies between the different ColdFire family members. Instead of keeping the base addresses with the UART definitions keep them with the other addresses definitions for each ColdFire part. The motivation for this move is so that when we add new ColdFire part definitions, they are all in a single file (and we shouldn't normally need to modify the UART definitions in mcfuart.h at all). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: fix clock rate value reported for ColdFire 54xx partsGreg Ungerer2011-01-051-1/+2
| | | | | | | | | | | The instruction timings of the ColdFire 54xx family parts are different to other version 4 parts (or version 2 or 3 parts for that matter too). Move the instruction timing setting into the ColdFire part specific headers, and set the 54xx value appropriately. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: move ColdFire CPU names into their headersGreg Ungerer2011-01-051-0/+1
| | | | | | | | | | Move the ColdFire CPU names out of setup.c and into their repsective headers. That way when we add new ones we won't need to modify setup.c any more. Add the missing 548x CPU name. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: Coldfire QSPI platform supportSteven King2010-05-171-0/+5
| | | | | | | | | | | Since Grant has added the coldfire-qspi driver to next-spi, here is the platform support for the parts that have qspi hardware. This sets up gpio to do the spi chip select using the default chip select pins; it should be trivial for boards that require different or additional spi chip selects to use other gpios as needed. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* generic GPIO support for the Freescale Coldfire 523x.sfking@fdwdc.com2009-09-101-0/+77
| | | | | | | Add support for the 523x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: move CPU reset code for the 523x ColdFire into its platform codeGreg Ungerer2009-06-111-0/+9
| | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68k,m68knommu: merge header filesSam Ravnborg2009-01-161-0/+45
Merge header files for m68k and m68knommu to the single location: arch/m68k/include/asm The majority of this patch was the result of the script that is included in the changelog below. The script was originally written by Arnd Bergman and exten by me to cover a few more files. When the header files differed the script uses the following: The original m68k file is named <file>_mm.h [mm for memory manager] The m68knommu file is named <file>_no.h [no for no memory manager] The files uses the following include guard: This include gaurd works as the m68knommu toolchain set the __uClinux__ symbol - so this should work in userspace too. Merging the header files for m68k and m68knommu exposes the (unexpected?) ABI differences thus it is easier to actually identify these and thus to fix them. The commit has been build tested with both a m68k and a m68knommu toolchain - with success. The commit has also been tested with "make headers_check" and this patch fixes make headers_check for m68knommu. The script used: TARGET=arch/m68k/include/asm SOURCE=arch/m68knommu/include/asm INCLUDE="cachectl.h errno.h fcntl.h hwtest.h ioctls.h ipcbuf.h \ linkage.h math-emu.h md.h mman.h movs.h msgbuf.h openprom.h \ oplib.h poll.h posix_types.h resource.h rtc.h sembuf.h shmbuf.h \ shm.h shmparam.h socket.h sockios.h spinlock.h statfs.h stat.h \ termbits.h termios.h tlb.h types.h user.h" EQUAL="auxvec.h cputime.h device.h emergency-restart.h futex.h \ ioctl.h irq_regs.h kdebug.h local.h mutex.h percpu.h \ sections.h topology.h" NOMUUFILES="anchor.h bootstd.h coldfire.h commproc.h dbg.h \ elia.h flat.h m5206sim.h m520xsim.h m523xsim.h m5249sim.h \ m5272sim.h m527xsim.h m528xsim.h m5307sim.h m532xsim.h \ m5407sim.h m68360_enet.h m68360.h m68360_pram.h m68360_quicc.h \ m68360_regs.h MC68328.h MC68332.h MC68EZ328.h MC68VZ328.h \ mcfcache.h mcfdma.h mcfmbus.h mcfne.h mcfpci.h mcfpit.h \ mcfsim.h mcfsmc.h mcftimer.h mcfuart.h mcfwdebug.h \ nettel.h quicc_simple.h smp.h" FILES="atomic.h bitops.h bootinfo.h bug.h bugs.h byteorder.h cache.h \ cacheflush.h checksum.h current.h delay.h div64.h \ dma-mapping.h dma.h elf.h entry.h fb.h fpu.h hardirq.h hw_irq.h io.h \ irq.h kmap_types.h machdep.h mc146818rtc.h mmu.h mmu_context.h \ module.h page.h page_offset.h param.h pci.h pgalloc.h \ pgtable.h processor.h ptrace.h scatterlist.h segment.h \ setup.h sigcontext.h siginfo.h signal.h string.h system.h swab.h \ thread_info.h timex.h tlbflush.h traps.h uaccess.h ucontext.h \ unaligned.h unistd.h" mergefile() { BASE=${1%.h} git mv ${SOURCE}/$1 ${TARGET}/${BASE}_no.h git mv ${TARGET}/$1 ${TARGET}/${BASE}_mm.h cat << EOF > ${TARGET}/$1 EOF git add ${TARGET}/$1 } set -e mkdir -p ${TARGET} git mv include/asm-m68k/* ${TARGET} rmdir include/asm-m68k git rm ${SOURCE}/Kbuild for F in $INCLUDE $EQUAL; do git rm ${SOURCE}/$F done for F in $NOMUUFILES; do git mv ${SOURCE}/$F ${TARGET}/$F done for F in $FILES ; do mergefile $F done rmdir arch/m68knommu/include/asm rmdir arch/m68knommu/include Cc: Arnd Bergmann <arnd@arndb.de> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Greg Ungerer <gerg@uclinux.org>