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* [MIPS] Define MIPS_CPU_IRQ_BASE in generic headerAtsushi Nemoto2007-02-061-5/+4
| | | | | | | | | | | | | | | | | | | | | | The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irqAtsushi Nemoto2006-11-301-0/+2
| | | | | | | | | | | | | | Further incorporation of generic irq framework. Replacing __do_IRQ() by proper flow handler would make the irq handling path a bit simpler and faster. * use generic_handle_irq() instead of __do_IRQ(). * use handle_level_irq for obvious level-type irq chips. * use handle_percpu_irq for irqs marked as IRQ_PER_CPU. * setup .eoi routine for irq chips possibly used with handle_percpu_irq. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] VSMP: Synchronize cp0 counters on bootup.Ralf Baechle2006-10-311-0/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] VSMP: Fix initialization ordering bug.Ralf Baechle2006-10-311-69/+83
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Complete fixes after removal of pt_regs argument to int handlers.Ralf Baechle2006-10-081-8/+8
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MT: Initialise all writable bits in Cause register to zero.Chris Dearman2006-09-271-1/+1
| | | | | | | | Recent 34Ks come out of reset with WP enabled on VPE 1 so we take an immediate exception when starting the second VPE. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [PATCH] irq-flags: MIPS: Use the new IRQF_ constantsThomas Gleixner2006-07-021-2/+2
| | | | | | | | | | | | Use the new IRQF_ constants and remove the SA_INTERRUPT define Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@elte.hu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [MIPS] FPU affinity for MT ASE.Ralf Baechle2006-04-191-0/+11
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MT: Improved multithreading support.Ralf Baechle2006-04-191-0/+349
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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