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* MIPS: O32: Fix ppollArnaud Patard2009-11-021-1/+1
| | | | | | | | sys_ppoll syscall needs to use a compat handler on 64bit kernels with o32 user-space. Signed-off-by: Arnaud Patard <apatard@mandriva.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Oprofile: Rename cpu_type from godson2 to loongson2Wu Zhangjin2009-11-021-1/+1
| | | | | | | | | | Unify the naming method between kernel and the user-space oprofile tool. Because loongson is used instead of godson in most of the places, we agreed to use loongson instead, which will simplify future maintenance. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Acked-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Fix hang with high-frequency edge interruptsManuel Lauss2009-11-021-8/+26
| | | | | | | | | | | | | | | | | The handle_edge_irq() flowhandler disables edge int sources which occur too fast (i.e. another edge comes in before the irq handler function had a chance to finish). Currently, the mask_ack() callback does not ack the edges in hardware, leading to an endless loop in the flowhandler where it tries to shut up the irq source. When I rewrote the alchemy IRQ code I wrongly assumed the mask_ack() callback was only used by the level flowhandler, hence it omitted the (at the time pointless) edge acks. Turned out I was wrong; so here is a complete mask_ack implementation for Alchemy IC, which fixes the above mentioned problem. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: TXx9: Fix spi-baseclk valueAtsushi Nemoto2009-11-021-1/+1
| | | | | | | | | | TXx9 SPI bit rate is calculated by: fBR = fSPI / 2 / (n + 1) (fSPI is SPI master clock freq, i.e. imbusclk freq.) So use imbus_clk / 2 as a spi-baseclk. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: bcm63xx: Set the correct BCM3302 CPU nameFlorian Fainelli2009-11-021-0/+3
| | | | | | | | For consistency with other BCM63xx SoC set the CPU name to "Broadcom BCM6338" when actually running on that system. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_storeZhang Le2009-11-021-2/+1
| | | | | | | | | | Loongson 2 does not have dcache aliases when is using 16k pages. and the And because Loongson 2 doesn't do SMP , cpu_icache_snoops_remote_store does not matter here. Signed-off-by: Zhang Le <r0bertz@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Avoid potential hazard on Context registerRalf Baechle2009-11-022-0/+4
| | | | | | | | | | set_saved_sp reads Context register. Avoid reading stale value from earlier incomplete write. Issue found and fixed for head.S by Chris Dearman <chris@mips.com>. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Use lockless interrupt controller operations when possible.David Daney2009-11-021-36/+178
| | | | | | | | Some newer Octeon chips have registers that allow lockless operation of the interrupt controller. Take advantage of them. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinityDavid Daney2009-11-021-4/+6
| | | | | | | | Since the locks are used from interrupt context we need the irqsave/irqrestore versions of the locking functions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Set S-cache linesize to 64-bytes for MTI's S-cacheRalf Baechle2009-11-021-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SMTC: Avoid queing multiple reschedule IPIsJaidev Patwardhan2009-11-022-4/+31
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: GCMP: Avoid accessing registers when they are not presentJaidev Patwardhan2009-11-021-3/+13
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: GIC: Random fixes and enhancements.Chris Dearman2009-11-025-293/+142
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_startChris Dearman2009-11-021-3/+4
| | | | | Signed-off-by: Chris Dearman (chris@mips.com) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operandsNigel Stephens2009-11-022-17/+7
| | | | | | | This patch ensures that the sign bit is always updated for NaN operands. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SPRAM: Clean up support code a littleChris Dearman2009-11-023-10/+12
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: 1004K: Enable SPRAM support.Ralf Baechle2009-11-021-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4Ralf Baechle2009-11-021-0/+13
| | | | | | Based on original patch by Chris Dearman <chris@mips.com>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.Ralf Baechle2009-11-021-2/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MTI: Fix accesses to device registers on MIPS boardsChris Dearman2009-11-021-1/+1
| | | | | | | | | This fixes the remaining problems introduced by f197465384bf7ef1af184c2ed1a4e268911a91e3 (incorrect access length & byteswapping in bigendian mode) Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix machine check exception in kmap_coherent()Kevin Cernekee2009-11-022-3/+7
| | | | | | | | | | | | | | | | | | | | | | | On an SMP system with cache aliases, the following sequence of events may happen: 1) copy_user_highpage() runs on CPU0, invoking kmap_coherent() to create a temporary mapping in the fixmap region 2) copy_page() starts on CPU0 3) CPU1 sends CPU0 an IPI asking CPU0 to run local_r4k_flush_cache_page() 4) CPU0 takes the interrupt, interrupting copy_page() 5) local_r4k_flush_cache_page() on CPU0 calls kmap_coherent() again 6) The second invocation of kmap_coherent() on CPU0 tries to use the same fixmap virtual address that was being used by copy_user_highpage() 7) CPU0 throws a machine check exception for the TLB address conflict Fixed by creating an extra set of fixmap entries for use in interrupt handlers. This prevents fixmap VA conflicts between copy_user_highpage() running in user context, and local_r4k_flush_cache_page() invoked from an SMP IPI. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MTX-1: Fix build if CONFIG_PCI is disabled.Ralf Baechle2009-11-021-2/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AR7: register watchdog device only if enabled in hw configurationFlorian Fainelli2009-11-022-1/+11
| | | | | | | | | This patch checks if the watchdog enable bit is set in the DCL register meaning that the hardware watchdog actually works and if so, register the ar7_wdt platform_device. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63xx: Prepare for watchdog supportFlorian Fainelli2009-11-022-1/+38
| | | | | | | | This patch prepares the board code to register a bcm63xx_wdt platform_device that we are going to use in a subsequent patch. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63xx: Make bcm63xx_uart_register an initfuncFlorian Fainelli2009-11-023-10/+1
| | | | | | | | | This patch removes the calls to bcm63xx_uart_register in board_bcm963xx.c and make bcm63xx_uart_register an initfunc. Allows us to remove bcm63xx_dev_uart.h which was there to make checkpatch.pl happy. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AU1000: Fix build failure for db1x00 configured for Au1100 SoCFlorian Fainelli2009-11-021-0/+2
| | | | | | | | | | | | This patch fixes the following warning, which becomes an error due to -Werror to be turned on: CC arch/mips/alchemy/common/gpiolib-au1000.o cc1: warnings being treated as errors arch/mips/alchemy/common/gpiolib-au1000.c: In function 'au1100_gpio2_to_irq': /home/florian/dev/kernel/linux-queue/arch/mips/include/asm/mach-au1x00/gpio-au1000.h:107: warning: control reaches end of non-void function Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63xx: Fix soft-reset lockup on BCM6345Florian Fainelli2009-11-021-1/+3
| | | | | | | | | | This patch fixes a lockup on BCM6345 where setting the PLL soft reset bit will also lock the other blocks including UART. Instead of setting only the PLL soft reset bit in the software reset register, set this bit but do not touch the others. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: TXx9: Fix error handling / Fix for noenexisting gpio_remove.Ralf Roesch2009-11-021-1/+2
| | | | | | | Error was introduced by commit 0385d1f3d394c6814be0b165c153fc3fc254469a. Signed-off-by: Ralf Roesch <ralf.roesch@rw-gmbh.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add IRQF_TIMER flag for timer interruptsWu Zhangjin2009-11-026-6/+6
| | | | | | | | | | | As the commit 3ee4c147 shows, we need to "Add IRQF_TIMER flag for timer interrupts", Atsushi Nemoto have reported that some other timer interrupts should be considered, Here it is. Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: 64-bit: Fix o32 lookup_dcookie syscallWu Zhangjin2009-11-022-1/+7
| | | | | | | | | | An o32 aplication passes a 64-bit value in a pair of registers; a 64-bit kernel expects a 64-bit argument in a single register. Signed-off-by: Chen Jie <chenj@lemote.com> Signed-off-by: Hu Hongbing <huhb@lemote.com> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: VPE: Remove stray unlock_kernel.Ralf Baechle2009-11-021-2/+0
| | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: Josip Rodin <joy@entuzijast.net>
* MIPS: Add IRQF_TIMER flag for timer interruptsWu Zhangjin2009-11-027-7/+7
| | | | | | | | | | Along the lines of d6c585a4342a2ff627a29f9aea77c5ed4cd76023, add IRQF_TIMER flag for all timer interrupts This ensures that timer interrupts won't be disabled on suspend and not threaded for PREEMPT_RT. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Remove redundant local_irq_disable()Wu Zhangjin2009-11-021-1/+0
| | | | | | | | That code is executed with irq disabled already, so, remove the redundant local_irq_disable() here. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IP27: Fix buildRalf Baechle2009-11-021-2/+2
| | | | | | Broken by 182a85f8a119c789610a9d464f4129ded9f3c107. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Cleanup CONFIG_DEBUG_STACK_USAGE version of alloc_thread_info.Ralf Baechle2009-11-021-8/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Fix compile error in arch/mips/cavium-octeon/smp.cDavid Daney2009-11-021-2/+3
| | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Don't write ones to reserved entryhi bits.Ralf Baechle2009-11-021-5/+5
| | | | | | | | | | | | | | | | We've silently been relying on the hardware chopping off excess, reserved ASID bits for no better reason that it saving an instruction. Because we already have: #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) in <asm/mmu_context.h>. We can use a cleanup to avoid writing non-zero bits into the reserved entryhi bits. This avoid triggering some debugging assertion in the Cavium simulator. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Extend COMMAND_LINE_SIZERalf Baechle2009-11-021-1/+1
| | | | | | Some firmware may pass well over 256 bytes these days. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Avoid spurious make includecheck messageRalf Baechle2009-09-301-2/+2
| | | | | | | | arch/mips/include/asm/unaligned.h: linux/unaligned/generic.h is included more than once. Entirely legitimate but just noise. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: VPE: Get rid of BKL.Ralf Baechle2009-09-302-42/+50
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: VPE: Fix build after the credential changes a while ago.Ralf Baechle2009-09-301-10/+23
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Excite: Get rid of BKL.Ralf Baechle2009-09-301-2/+0
| | | | | | It's not obvious what good it was supposed to do here anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Sibyte: Get rid of BKL.Ralf Baechle2009-09-301-18/+15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63xx: Add PCMCIA & Cardbus support.Maxime Bizon2009-09-304-1/+162
| | | | | | Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MSP71xx: request_irq() failure ignored in msp_pcibios_config_access()Roel Kluin2009-09-301-1/+4
| | | | | | | | | Produce an error if request_irq() fails. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Cc: "Ithamar R. Adema" <ithamar.adema@team-embedded.nl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Decrease size of au1xxx_dbdma_pm_regs[][]Roel Kluin2009-09-301-5/+3
| | | | | | | | | | | There are 16 individual channels (NUM_DBDMA_CHANS) to save/restore plus the global ddma block config (the +1). The last register in a channel can be skipped since it's read-only (at offset 0x18). Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Cc: Manuel Lauss <manuel.lauss@googlemail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SMP: Inline arch_send_call_function_{single_ipi,ipi_mask}Ralf Baechle2009-09-302-15/+13
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SMP: Fix build.Ralf Baechle2009-09-302-2/+2
| | | | | | | | | | commit 48a048fed82a8e5fdd8618574f6d3de1a0d67a50 Author: Rusty Russell <rusty@rustcorp.com.au> Date: Thu Sep 24 09:34:44 2009 -0600 apparently only passed the "looks good" level of QA ;-) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.Kevin Cernekee2009-09-301-0/+5
| | | | | | | | This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover MIPSxx-style board cache code. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Sibyte: Fix compilation error.Mark Mason2009-09-301-1/+1
| | | | | | | Build error introduced by d4f587c67fc39e0030ddd718675e252e208da4d7. Signed-off-by: Mark Mason <mmason@upwardaccess.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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