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path: root/arch/powerpc/boot/dts/p2020rdb.dts
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* ptp: Added a clock that uses the eTSEC found on the MPC85xx.Richard Cochran2011-05-231-0/+13
| | | | | | | | | | | The eTSEC includes a PTP clock with quite a few features. This patch adds support for the basic clock adjustment functions, plus two external time stamps, one alarm, and the PPS callback. Signed-off-by: Richard Cochran <richard.cochran@omicron.at> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: John Stultz <john.stultz@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org>
* powerpc/85xx: Fix PCIe IDSEL for Px020RDBPrabhakar Kushwaha2011-05-191-0/+16
| | | | | | | | | | | | | | PCIe device in legacy mode can trigger interrupts using the wires #INTA, #INTB ,#INTC and #INTD. PCI devices are obligated to use #INTx for interrupts under legacy mode. Each PCI slot or device is typically wired to different inputs on the interrupt controller. So, Define interrupt-map and interrupt-map-mask properties for device tree to of map each PCI interrupt signal to the inputs of the interrupt controller. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: P2020 DTS: re-organize dts filesPrabhakar Kushwaha2011-05-191-332/+30
| | | | | | | | Creates P2020si.dtsi, containing information for P2020 SoC. Modifies dts files for P2020 based systems to use dtsi file. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Update dts for PCIe memory maps to match u-boot of Px020RDBPrabhakar Kushwaha2011-04-041-6/+6
| | | | | | | | | | PCIe memory address space is 1:1 mapped with u-boot. Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map changes in u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for P2020RDB boardPoonam Aggrwal2009-08-241-0/+586
Add support for the P2020RDB reference board from Freescale. Overview of P2020RDB platform - DDR DDR2 1G - NOR Flash 16MByte - NAND Flash 32MByte - 3 Ethernet interfaces 1) etSEC1 - RGMII - connected to a 5 port Vitesse Switch(VSC7385) - Switch is memory mapped through eLBC interface(CS#2) - IRQ1 2) etSEC2 - SGMII - connected to VSC8221 - IRQ2 3) etSEC3 - RGMII - connected to VSC8641 - IRQ3 - 2 1X PCIe interfaces - SD/MMC ,USB - SPI EEPROM - Serial I2C EEPROM Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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