| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | powerpc/book3e-64: use a separate TLB handler when linear map is bolted | Scott Wood | 2011-06-29 | 1 | -18/+34 |
| | | | | | | | | | | | | | | | | | | On MMUs such as FSL where we can guarantee the entire linear mapping is bolted, we don't need to worry about linear TLB misses. If on top of that we do a full table walk, we get rid of all recursive TLB faults, and can dispense with some state saving. This gains a few percent on TLB-miss-heavy workloads, and around 50% on a benchmark that had a high rate of virtual page table faults under the normal handler. While touching the EX_TLB layout, remove EX_TLB_MMUCR0, EX_TLB_SRR0, and EX_TLB_SRR1 as they're not used. [BenH: Fixed build with 64K pages (wsp config)] Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> | ||||
| * | powerpc/book3e-64: Add helper function to setup IVORs | Kumar Gala | 2009-08-28 | 1 | -0/+4 |
| | | | | | | | | | | | Not all 64-bit Book-3E parts will have fixed IVORs so add a function that cpusetup code can call to setup the base IVORs (0..15) to match the fixed offsets. We need to 'or' part of interrupt_base_book3e into the IVORs since on parts that have them the IVPR doesn't extend as far down. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> | ||||
| * | powerpc: Add definitions used by exception handling on 64-bit Book3E | Benjamin Herrenschmidt | 2009-08-20 | 1 | -0/+201 |
| This adds various definitions and macros used by the exception and TLB miss handling on 64-bit BookE It also adds the definitions of the SPRGs used for various exception types Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> | |||||
 |
index : kernel_samsung_smdk4412.git | |
| kernel for Galaxy S3 |
| aboutsummaryrefslogtreecommitdiffstats |