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* sparc/irqs: Do not trace arch_local_{*,irq_*} functionsSteven Rostedt2011-07-062-11/+11
| | | | | | | | | | | | | Do not trace arch_local_save_flags(), arch_local_irq_*() and friends. Although they are marked inline, gcc may still make a function out of them and add it to the pool of functions that are traced by the function tracer. This can cause undesirable results (kernel panic, triple faults, etc). Add the notrace notation to prevent them from ever being traced. Signed-off-by: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* Fix node_start/end_pfn() definition for mm/page_cgroup.cKAMEZAWA Hiroyuki2011-06-271-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 21a3c96 uses node_start/end_pfn(nid) for detection start/end of nodes. But, it's not defined in linux/mmzone.h but defined in /arch/???/include/mmzone.h which is included only under CONFIG_NEED_MULTIPLE_NODES=y. Then, we see mm/page_cgroup.c: In function 'page_cgroup_init': mm/page_cgroup.c:308: error: implicit declaration of function 'node_start_pfn' mm/page_cgroup.c:309: error: implicit declaration of function 'node_end_pfn' So, fixiing page_cgroup.c is an idea... But node_start_pfn()/node_end_pfn() is a very generic macro and should be implemented in the same manner for all archs. (m32r has different implementation...) This patch removes definitions of node_start/end_pfn() in each archs and defines a unified one in linux/mmzone.h. It's not under CONFIG_NEED_MULTIPLE_NODES, now. A result of macro expansion is here (mm/page_cgroup.c) for !NUMA start_pfn = ((&contig_page_data)->node_start_pfn); end_pfn = ({ pg_data_t *__pgdat = (&contig_page_data); __pgdat->node_start_pfn + __pgdat->node_spanned_pages;}); for NUMA (x86-64) start_pfn = ((node_data[nid])->node_start_pfn); end_pfn = ({ pg_data_t *__pgdat = (node_data[nid]); __pgdat->node_start_pfn + __pgdat->node_spanned_pages;}); Changelog: - fixed to avoid using "nid" twice in node_end_pfn() macro. Reported-and-acked-by: Randy Dunlap <randy.dunlap@oracle.com> Reported-and-tested-by: Ingo Molnar <mingo@elte.hu> Acked-by: Mel Gorman <mgorman@suse.de> Signed-off-by: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* sparc32, leon: bugfix in LEON SMP interrupt initDaniel Hellstrom2011-06-091-0/+16
| | | | | | | | | | | | | | | During converting per-cpu ticker to genirq layer some IRQ initialization code was removed by commit 2cf9530420e446bb61f665d02afeb81070106900 ("sparc32,leon: per-cpu ticker use genirq per-cpu handler"). This patch reintroduces the code at the same place it was removed from. IRQ12 - IRQ14 will crash on LEON SMP without this patch because it will run the SUN4M IRQ trap handler. Reported-by: Jan Andersson <jan@gaisler.com> Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc32, sun4m: bugfix in SMP IPI traphandlerDaniel Hellstrom2011-06-091-2/+2
| | | | | | | | | | | | | | | | Three new IPIs were introduced by commit ecbc42b70acbc6327adefe9635db93fcf62bf59d ("sparc32, sun4m: Implemented SMP IPIs support for SUN4M machines"), the old handler was already prepared for IPIs but handled only IRQ14 and IRQ13, this patch adds support for the new IPI at IRQ12. The IPI trap handler looks at the mask rather than the pending IRQ/IPI, this bug may have masked the problem above, introduced by the same commit. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc: Remove unnecessary semicolonsJoe Perches2011-06-0734-65/+65
| | | | | | | | Semicolons are not necessary after switch/while/for/if braces so remove them. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Add support for allocating irqs for bootbus devicesoftedal2011-06-071-12/+22
| | | | | | | | | | | Some devices that can generate interrupts are connected directly to the CPU through the bootbus on sun4d. This patch allows IRQs to be allocated for such devices. The information used for allocating interrupts for sbus devices are present at the corresponding SBI node. For bootbus devices this information is present in the bootbus node. Signed-off-by: Kjetil Oftedal <oftedal@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Do not skip interrupt sources in sun4d interrupt handler and acknowledge ↵oftedal2011-06-071-9/+5
| | | | | | | | | | | | | | | | | | | | | | | interrupts correctly During the introduction of genirq on sparc32 bugs were introduced in the interrupt handler for sun4d. The interrupts handler checks the status of the various sbus interfaces in the system and generates a virtual interrupt, based upon the location of the interrupt source. This lookup was broken by restructuring the code in such a way that index and shift operations were performed prior to comparing this against the values read from the interrupt controllers. This could cause the handler to loop eternally as the interrupt source could be skipped before any check was performed. Additionally sun4d_encode_irq performs shifting internally, so it should not be performed twice. In sun4d_unmask interrupts were not correctly acknowledged, as the corresponding bit it the interrupt mask was not actually cleared. Signed-off-by: Kjetil Oftedal <oftedal@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Restructure sun4d_build_device_irq so that timer interrupts can be allocatedoftedal2011-06-071-24/+54
| | | | | | | | | | | | | | | sun4d_build_device_irq was called without a valid platform_device when the system timer was initialized on sun4d systems. This caused a NULL pointer crash. Josip Rodin suggested that the current sun4d_build_device_irq should be split into two functions. So that the timer initialization could skip the slot and sbus interface detection code in sun4d_build_device_irq, as this does not make sence due to the timer interrupts not being generated from a device located on sbus. Signed-off-by: Kjetil Oftedal <oftedal@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc: PCIC_PCI needs SPARC32 dependencyDavid S. Miller2011-06-021-1/+1
| | | | | Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc: Do not select GENERIC_HARDIRQS_NO_DEPRECATEDGeert Uytterhoeven2011-06-021-1/+0
| | | | | | | | | | | Config option GENERIC_HARDIRQS_NO_DEPRECATED was removed in commit 78c89825649a9a5ed526c507603196f467d781a5 ("genirq: Remove the now obsolete config options and select statements"), but the select was accidentally reintroduced in commit 6baa9b20a68a88c2fd751cbe8d7652009379351b ("sparc32: genirq support") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc32,leon: add GRPCI2 PCI Host driverDaniel Hellstrom2011-06-025-0/+923
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA region must be accessible in order for PCI peripheral drivers to work, the sparc32 has DMA in the normal memory zone which requires the GRPCI2 to PCI target BARs so that all kernel low mem (192MB) can be mapped 1:1 to PCI address space. The GRPCI2 has resizeable target BARs, by default the first is made 256MB and all other BARs are disabled. I/O space are always located on 0x1000-0x10000, but accessed through the GRPCI2 PCI I/O Window memory mapped to virtual address space. Configuration space is accessed through the 64KB GRPCI2 PCI CFG Window using LDA bypassing the MMU. The GRPCI2 has a single PCI Window for prefetchable and non- prefetchable address space, it is up to the AHB master requesting PCI data to determine access type. Memory space is mapped 1:1. The GRPCI2 core can be configured in 4 different IRQ modes, where PCI Interrupt, Error Interrupt and DMA Interrupt are shared on a single IRQ line or at most 5 IRQs are used. The GRPCI2 can mask/unmask PCI interrupts, Err and DMA in the control and check status bits which tells us which IRQ really happended. The GENIRQ layer is used to unmask/mask each individual IRQ source by creating virtual IRQs and implementing a IRQ chip. The optional DMA functionality of the GRPCI2 is not supported by this patch. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc32,leon: added LEON-common low-level PCI routinesDaniel Hellstrom2011-06-025-0/+304
| | | | | | | | | The LEON architecture does not have a BIOS or bootloader that initializes PCI for us, instead Linux generic PCI layer is used to set up resources and IRQ. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* sparc32: added CONFIG_PCIC_PCI Kconfig settingDaniel Hellstrom2011-06-024-4/+9
| | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge branch 'setns'Linus Torvalds2011-05-283-4/+5
|\ | | | | | | | | | | | | | | * setns: ns: Wire up the setns system call Done as a merge to make it easier to fix up conflicts in arm due to addition of sendmmsg system call
| * ns: Wire up the setns system callEric W. Biederman2011-05-283-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 32bit and 64bit on x86 are tested and working. The rest I have looked at closely and I can't find any problems. setns is an easy system call to wire up. It just takes two ints so I don't expect any weird architecture porting problems. While doing this I have noticed that we have some architectures that are very slow to get new system calls. cris seems to be the slowest where the last system calls wired up were preadv and pwritev. avr32 is weird in that recvmmsg was wired up but never declared in unistd.h. frv is behind with perf_event_open being the last syscall wired up. On h8300 the last system call wired up was epoll_wait. On m32r the last system call wired up was fallocate. mn10300 has recvmmsg as the last system call wired up. The rest seem to at least have syncfs wired up which was new in the 2.6.39. v2: Most of the architecture support added by Daniel Lezcano <dlezcano@fr.ibm.com> v3: ported to v2.6.36-rc4 by: Eric W. Biederman <ebiederm@xmission.com> v4: Moved wiring up of the system call to another patch v5: ported to v2.6.39-rc6 v6: rebased onto parisc-next and net-next to avoid syscall conflicts. v7: ported to Linus's latest post 2.6.39 tree. >  arch/blackfin/include/asm/unistd.h     |    3 ++- >  arch/blackfin/mach-common/entry.S      |    1 + Acked-by: Mike Frysinger <vapier@gentoo.org> Oh - ia64 wiring looks good. Acked-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | arch: remove CONFIG_GENERIC_FIND_{NEXT_BIT,BIT_LE,LAST_BIT}Akinobu Mita2011-05-261-8/+0
|/ | | | | | | | | | | | | | | By the previous style change, CONFIG_GENERIC_FIND_NEXT_BIT, CONFIG_GENERIC_FIND_BIT_LE, and CONFIG_GENERIC_FIND_LAST_BIT are not used to test for existence of find bitops anymore. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Acked-by: Greg Ungerer <gerg@uclinux.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* lib: consolidate DEBUG_STACK_USAGE optionStephen Boyd2011-05-251-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Most arches define CONFIG_DEBUG_STACK_USAGE exactly the same way. Move it to lib/Kconfig.debug so each arch doesn't have to define it. This obviously makes the option generic, but that's fine because the config is already used in generic code. It's not obvious to me that sysrq-P actually does anything caution by keeping the most inclusive wording. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Chris Metcalf <cmetcalf@tilera.com> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Richard Weinberger <richard@nod.at> Acked-by: Mike Frysinger <vapier@gentoo.org> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Hirokazu Takata <takata@linux-m32r.org> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Mackerras <paulus@samba.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Chen Liqin <liqin.chen@sunplusct.com> Cc: Lennox Wu <lennox.wu@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* mm: now that all old mmu_gather code is gone, remove the storagePeter Zijlstra2011-05-251-2/+0
| | | | | | | | | | | | | | | | | | | | | | Fold all the mmu_gather rework patches into one for submission Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Reported-by: Hugh Dickins <hughd@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: David Miller <davem@davemloft.net> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Jeff Dike <jdike@addtoit.com> Cc: Richard Weinberger <richard@nod.at> Cc: Tony Luck <tony.luck@intel.com> Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Cc: Mel Gorman <mel@csn.ul.ie> Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Cc: Nick Piggin <npiggin@kernel.dk> Cc: Namhyung Kim <namhyung@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* sparc: mmu_gather reworkPeter Zijlstra2011-05-256-116/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework the sparc mmu_gather usage to conform to the new world order :-) Sparc mmu_gather does two things: - tracks vaddrs to unhash - tracks pages to free Split these two things like powerpc has done and keep the vaddrs in per-cpu data structures and flush them on context switch. The remaining bits can then use the generic mmu_gather. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by: David Miller <davem@davemloft.net> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Jeff Dike <jdike@addtoit.com> Cc: Richard Weinberger <richard@nod.at> Cc: Tony Luck <tony.luck@intel.com> Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Cc: Hugh Dickins <hughd@google.com> Cc: Mel Gorman <mel@csn.ul.ie> Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Cc: Nick Piggin <npiggin@kernel.dk> Cc: Namhyung Kim <namhyung@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* arch, mm: filter disallowed nodes from arch specific show_mem functionsDavid Rientjes2011-05-252-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Architectures that implement their own show_mem() function did not pass the filter argument to show_free_areas() to appropriately avoid emitting the state of nodes that are disallowed in the current context. This patch now passes the filter argument to show_free_areas() so those nodes are now avoided. This patch also removes the show_free_areas() wrapper around __show_free_areas() and converts existing callers to pass an empty filter. ia64 emits additional information for each node, so skip_free_areas_zone() must be made global to filter disallowed nodes and it is converted to use a nid argument rather than a zone for this use case. Signed-off-by: David Rientjes <rientjes@google.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Luck <tony.luck@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Kyle McMartin <kyle@mcmartin.ca> Cc: Helge Deller <deller@gmx.de> Cc: James Bottomley <jejb@parisc-linux.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'for-2.6.40' of ↵Linus Torvalds2011-05-241-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu * 'for-2.6.40' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu: percpu: Unify input section names percpu: Avoid extra NOP in percpu_cmpxchg16b_double percpu: Cast away printk format warning percpu: Always align percpu output section to PAGE_SIZE Fix up fairly trivial conflict in arch/x86/include/asm/percpu.h as per Tejun
| * Merge branch 'fixes-2.6.39' into for-2.6.40Tejun Heo2011-05-242-1/+5
| |\
| * | percpu: Always align percpu output section to PAGE_SIZETejun Heo2011-03-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Percpu allocator honors alignment request upto PAGE_SIZE and both the percpu addresses in the percpu address space and the translated kernel addresses should be aligned accordingly. The calculation of the former depends on the alignment of percpu output section in the kernel image. The linker script macros PERCPU_VADDR() and PERCPU() are used to define this output section and the latter takes @align parameter. Several architectures are using @align smaller than PAGE_SIZE breaking percpu memory alignment. This patch removes @align parameter from PERCPU(), renames it to PERCPU_SECTION() and makes it always align to PAGE_SIZE. While at it, add PCPU_SETUP_BUG_ON() checks such that alignment problems are reliably detected and remove percpu alignment comment recently added in workqueue.c as the condition would trigger BUG way before reaching there. For um, this patch raises the alignment of percpu area. As the area is in .init, there shouldn't be any noticeable difference. This problem was discovered by David Howells while debugging boot failure on mn10300. Signed-off-by: Tejun Heo <tj@kernel.org> Acked-by: Mike Frysinger <vapier@gentoo.org> Cc: uclinux-dist-devel@blackfin.uclinux.org Cc: David Howells <dhowells@redhat.com> Cc: Jeff Dike <jdike@addtoit.com> Cc: user-mode-linux-devel@lists.sourceforge.net
* | | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next-2.6Linus Torvalds2011-05-2253-1678/+1552
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next-2.6: (28 commits) sparc32: fix build, fix missing cpu_relax declaration SCHED_TTWU_QUEUE is not longer needed since sparc32 now implements IPI sparc32,leon: Remove unnecessary page_address calls in LEON DMA API. sparc: convert old cpumask API into new one sparc32, sun4d: Implemented SMP IPIs support for SUN4D machines sparc32, sun4m: Implemented SMP IPIs support for SUN4M machines sparc32,leon: Implemented SMP IPIs for LEON CPU sparc32: implement SMP IPIs using the generic functions sparc32,leon: SMP power down implementation sparc32,leon: added some SMP comments sparc: add {read,write}*_be routines sparc32,leon: don't rely on bootloader to mask IRQs sparc32,leon: operate on boot-cpu IRQ controller registers sparc32: always define boot_cpu_id sparc32: removed unused code, implemented by generic code sparc32: avoid build warning at mm/percpu.c:1647 sparc32: always register a PROM based early console sparc32: probe for cpu info only during startup sparc: consolidate show_cpuinfo in cpu.c sparc32,leon: implement genirq CPU affinity ...
| * | | sparc32: fix build, fix missing cpu_relax declarationSam Ravnborg2011-05-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following sparc (32 bit) build error: CC arch/sparc/kernel/asm-offsets.s In file included from include/linux/seqlock.h:29:0, from include/linux/time.h:8, from include/linux/timex.h:56, from include/linux/sched.h:57, from arch/sparc/kernel/asm-offsets.c:13: include/linux/spinlock.h: In function 'spin_unlock_wait': include/linux/spinlock.h:360:2: error: implicit declaration of function 'cpu_relax' Most likely caused by commit e66eed651fd1 ("list: remove prefetching from regular list iterators") due to include changes. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | Merge commit '317f394160e9beb97d19a84c39b7e5eb3d7815a8'David S. Miller2011-05-202-4/+5
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/sparc/kernel/smp_32.c With merge conflict help from Daniel Hellstrom. Signed-off-by: David S. Miller <davem@davemloft.net>
| * \ \ \ Merge branch 'master' of ↵David S. Miller2011-05-206-9/+32
| |\ \ \ \ | | | | | | | | | | | | | | | | | | master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
| | * | | | sparc: add {read,write}*_be routinesJan Andersson2011-05-121-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds {read,write}*_be big endian memory access routines to the io.h header used on SPARC32 and SPARC64. Tested on SPARC32 (LEON) Signed-off-by: Jan Andersson <jan@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32,leon: Remove unnecessary page_address calls in LEON DMA API.Kristoffer Glembo2011-05-161-26/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function mmu_inval_dma_area takes a virtual address as a parameter which is problematic in case the buffer is located in highmem and the mapping currently is unavailable. Since the function was only implemented for LEON this patch removes calls to it in non LEON code paths and renames it to dma_make_coherent which instead takes a physical address (which for now is unused since we flush the whole cache). This way it is possible to remove several unnecessary calls to page_address which will fail if the virtual mapping is unavailable. Signed-off-by: Kristoffer Glembo <kristoffer@gaisler.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc: convert old cpumask API into new oneKOSAKI Motohiro2011-05-1616-105/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adapt new API. Almost change is trivial, most important change are to remove following like =operator. cpumask_t cpu_mask = *mm_cpumask(mm); cpus_allowed = current->cpus_allowed; Because cpumask_var_t is =operator unsafe. These usage might prevent kernel core improvement. No functional change. Signed-off-by: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32, sun4d: Implemented SMP IPIs support for SUN4D machinesDaniel Hellstrom2011-05-163-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sun4d does not seem to have a distingstion between soft and hard IRQs. When generating IPIs the generated IRQ looks like a hard IRQ, this patch adds a "IPI check" in the sun4d irq trap handler at a predefined IRQ number (SUN4D_IPI_IRQ). Before generating an IPI a per-cpu memory structure is modified for the "IPI check" to successfully detect a IPI request to a specific processor, the check clears the IPI work requested. All three IPIs (resched, single and cpu-mask) use the same IRQ number. The IPI IRQ should preferrably be on a separate IRQ and definitly not shared with IRQ handlers requesting IRQ with IRQF_SHARED. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32, sun4m: Implemented SMP IPIs support for SUN4M machinesDaniel Hellstrom2011-05-163-9/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the three IPIs (resched, single and cpu-mask) generation and interrupt handler catch. The sun4m has 15 soft-IRQs and three of them is used with this patch, the three IPIs was previously implemented with the cross-call IRQ15 which does not work with locking routines such as spinlocks because IRQ15 is NMI, it may cause deadlock. The IRQ trap handler code assumes (in the same spritit as the old it seems) that hard interrupts will be generated until handled (level), when a IRQ happens the IRQ pending register is checked for pending soft-IRQs. When both hard and soft IRQ happens at the same time only soft-IRQs are handled. The old code implemented a soft-IRQ traphandler at IRQ14 which called smp_reschedule_irq which in turn called set_need_resched. It seems to be an old relic and is replaced with the interrupt traphander exit code RESTORE_ALL, it calls schedule() when appropriate. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32,leon: Implemented SMP IPIs for LEON CPUDaniel Hellstrom2011-05-163-3/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements SMP IPIs on LEON using software generated IRQs to signal between CPUs. The IPI IRQ number is set by using the ipi_num property in the device tree, or defaults to 13. LEON SMP systems should reserve IRQ 13 (and IRQ 15) to Linux in order for the defaults to work. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32: implement SMP IPIs using the generic functionsDaniel Hellstrom2011-05-165-16/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current sparc32 SMP IPI generation is implemented the cross call function. The cross call function uses IRQ15 the NMI, this is has the effect that IPIs will interrupt IRQ critical areas and hang the system. Typically on/after spin_lock_irqsave calls can be aborted. The cross call functionality must still exist to flush cache/TLBS. This patch provides CPU models a custom way to implement generation of IPIs on the generic code's request. The typical approach is to generate an IRQ for each IPI case. After this patch each sparc32 SMP CPU model needs to implement IPIs in order to function properly. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32,leon: SMP power down implementationDaniel Hellstrom2011-05-161-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32,leon: added some SMP commentsDaniel Hellstrom2011-05-162-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32,leon: don't rely on bootloader to mask IRQsDaniel Hellstrom2011-04-212-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32,leon: operate on boot-cpu IRQ controller registersDaniel Hellstrom2011-04-213-25/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * proper initialization of boot_cpu_id (no hardcoding to 0) * use boot_cpu_id index to address into the IRQ controller where appropriate Each CPU has a separate set of IRQ controller registers, this patch makes sure that the boot-cpu registers are used instead of CPU0's. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32: always define boot_cpu_idDaniel Hellstrom2011-04-215-14/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define boot_cpu_id in single-processor kernels as well. This is to support architectures which can boot on other than CPU0. Sam Ravnborg has written the cleanup parts by extracting boot_cpu_id from smp_32.c into setup_32.c and cleaned up sun4d_irq.c. boot_cpu_id was initialized before BSS was cleared in sun4c_continue_boot, instead boot_cpu_id is set to 0xff to avoid BSS. If boot_cpu_id is untouched (0xff) by bootup code it will be overwritten to 0. boot_cpu_id4 is automatically calculated in common code. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32: removed unused code, implemented by generic codeDaniel Hellstrom2011-04-212-205/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32: avoid build warning at mm/percpu.c:1647Sam Ravnborg2011-04-211-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following warning: mm/percpu.c: In function 'pcpu_embed_first_chunk': mm/percpu.c:1647:3: warning: format '%lx' expects type 'long unsigned int', but argument 3 has type 'unsigned int' Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> [sam: added warning message to changelog, use _AC()] Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32: always register a PROM based early consoleSam Ravnborg2011-04-213-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not require user to add "-p" to boot arguments to see early info printed to prom console. This is similar to the sparc64 functionality - which was added with: 3c62a2d3477ff7725210db57aec3d2806fa10c20 ("[SPARC64]: Always register a PROM based early console.") Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32: probe for cpu info only during startupSam Ravnborg2011-04-216-13/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We did a cpu_probe() call each time a CPU got online - which only effect was to save latest CPU/FPU info for use by show_cpuinfo(). Use same setup as for sparc64 where we probe for this info during startup, and only once. This allowed us to annotate a few functions __init which again fixed the following section mismatch warnings: WARNING: vmlinux.o(.text+0x65f0): Section mismatch in reference from the function set_cpu_and_fpu() to the (unknown reference) .init.rodata:(unknown) WARNING: vmlinux.o(.text+0x65f8): Section mismatch in reference from the function set_cpu_and_fpu() to the (unknown reference) .init.rodata:(unknown) WARNING: vmlinux.o(.text+0x664c): Section mismatch in reference from the function set_cpu_and_fpu() to the variable .init.rodata:manufacturer_info WARNING: vmlinux.o(.text+0x6650): Section mismatch in reference from the function set_cpu_and_fpu() to the variable .init.rodata:manufacturer_info Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc: consolidate show_cpuinfo in cpu.cSam Ravnborg2011-04-218-157/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have all the cpu related info in cpu.c - so move the remaining functions to support /proc/cpuinfo to this file. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32,leon: implement genirq CPU affinityDaniel Hellstrom2011-04-211-10/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A simple implementation of CPU affinity, the first CPU in the affinity CPU mask always takes the IRQ. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32, leon: code cleanup of timer/IRQ controller initializationDaniel Hellstrom2011-04-211-84/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleaned up leon_init_timers() by removing unnecessary double checking and one indentation level. Changed LEON_IMASK to LEON_IMASK(cpu). Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32,leon: cleaned away code from the LEON2 daysDaniel Hellstrom2011-04-212-24/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32,leon: per-cpu ticker use genirq per-cpu handlerDaniel Hellstrom2011-04-214-51/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32,leon: add support for extended interrupt controllerDaniel Hellstrom2011-04-212-28/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The extended IRQ controller gives the LEON 16 more IRQs. The patch installs a custom handler for the exetended controller IRQ, where a register is read and the "real" IRQ causing IRQ is determined. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | sparc32, leon: must protect IRQ controller register with spinlockDaniel Hellstrom2011-04-211-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LEON interrupt controller has one single mask register for all IRQs per CPU, even though the genirq layer protects us from accessing the same IRQ at the same time other IRQs share the same mask register and may thus interfere. Some other IRQ controllers has a mask register or similar per IRQ instead which makes spinlocks unncessary. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
generated by cgit v1.1 at 2024-05-17 19:06:55 +0000