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* Board smdk4x12: Add androidboot.hardware=smdk4x12 to kernel cmdlinerogersb112015-10-234-12/+12
| | | | Change-Id: If3b1181253a7dbdb839146b3793ceee5e31fae6e
* ARM: Exynos: Call cpu_pm_enter/exit in Low Power States.Christian Neumüller2015-07-011-0/+9
| | | | | | | | | | | | | | | In low power cpuidle states, the FPU registers get corrupted. By calling cpu_pm_enter, the VFP module gets notified so that it saves the FPU state and restores it from RAM the next time a thread uses it. The comments at cpu_pm_enter/exit indicate that these functions must be called with interrupts disabled, so place the calls between local_irq_disable/local_irq_enble. See http://forum.xda-developers.com/showthread.php?p=57637134 to http://forum.xda-developers.com/showthread.php?p=57643086. Change-Id: Icde0ab93734cf2a4febfabc3c04e77ce955bd9da
* ARM: gic: Use cpu pm notifiers to save gic stateColin Cross2015-07-011-0/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | When the cpu is powered down in a low power mode, the gic cpu interface may be reset, and when the cpu cluster is powered down, the gic distributor may also be reset. This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save and restore the gic cpu interface registers, and the CPU_CLUSTER_PM_ENTER and CPU_CLUSTER_PM_EXIT notifiers to save and restore the gic distributor registers. Merge note: Samsung had already applied the changes to struct gic_chip_data, although it still remains in the .c file instead of having been moved to the header. Original-author: Gary King <gking@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Conflicts: arch/arm/include/asm/hardware/gic.h Change-Id: I50b5cdd161637ff7b871ac5ffb30d669ec60c662
* ARM: Enable CPU_PM notifiers on ARM machines.Santosh Shilimkar2015-07-011-0/+1
| | | | | | | Change-Id: Ifecfa0399e7fca47c43e4f24225448d6ff3780f4 Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
* ARM: 7873/1: vfp: clear vfp_current_hw_state for dying cpuYuanyuan Zhong2015-07-011-3/+3
| | | | | | | | | | | | The CPU_DYING notifier is called by cpu stopper task which does not own the context held in the VFP hardware. Calling vfp_force_reload() has no effect. Replace it with clearing vfp_current_hw_state. Change-Id: If6ea6b94e04dc4588c5bf2ec0fad4d0dcc49ffd6 Signed-off-by: Yuanyuan Zhong <zyy@motorola.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Lanchon <lanchon@gmail.com>
* ARM: 7419/1: vfp: fix VFP flushing regression on sigreturn pathWill Deacon2015-07-011-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | Commit ff9a184c ("ARM: 7400/1: vfp: clear fpscr length and stride bits on entry to sig handler") flushes the VFP state prior to entering a signal handler so that a VFP operation inside the handler will trap and force a restore of ABI-compliant registers. Reflushing and disabling VFP on the sigreturn path is predicated on the saved thread state indicating that VFP was used by the handler -- however for SMP platforms this is only set on context-switch, making the check unreliable and causing VFP register corruption in userspace since the register values are not necessarily those restored from the sigframe. This patch unconditionally flushes the VFP state after a signal handler. Since we already perform the flush before the handler and the flushing itself happens lazily, the redundant flush when VFP is not used by the handler is essentially a nop. Change-Id: Ia9ec6384fae3281def1dc93914af336857a09949 Reported-by: Jon Medhurst <tixy@linaro.org> Signed-off-by: Jon Medhurst <tixy@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Lanchon <lanchon@gmail.com>
* ARM: 7400/1: vfp: clear fpscr length and stride bits on entry to sig handlerWill Deacon2015-07-011-1/+21
| | | | | | | | | | | | | | | | | | | | | The ARM PCS mandates that the length and stride bits of the fpscr are cleared on entry to and return from a public interface. Although signal handlers run asynchronously with respect to the interrupted function, the handler itself expects to run as though it has been called like a normal function. This patch updates the state mirroring the VFP hardware before entry to a signal handler so that it adheres to the PCS. Furthermore, we disable VFP to ensure that we trap on any floating point operation performed by the signal handler and synchronise the hardware appropriately. A check is inserted after the signal handler to avoid redundant flushing if VFP was not used. Change-Id: Ic16296179773f609e2768c89756a0abece1a3247 Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Lanchon <lanchon@gmail.com>
* ARM: 7399/1: vfp: move user vfp state save/restore code out of signal.cWill Deacon2015-07-013-51/+90
| | | | | | | | | | | | | | The user VFP state must be preserved (subject to ucontext modifications) across invocation of a signal handler and this is currently handled by vfp_{preserve,restore}_context in signal.c Since this code requires intimate low-level knowledge of the VFP state, this patch moves it into vfpmodule.c. Change-Id: Ib82f326e7815d139b696d1db6a357769b449c1f3 Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Lanchon <lanchon@gmail.com>
* ARM: vfp: Use cpu pm notifiers to save vfp stateColin Cross2015-07-011-8/+21
| | | | | | | | | | | | | | | | When the cpu is powered down in a low power mode, the vfp registers may be reset. This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save and restore the cpu's vfp registers. Change-Id: I805e18a5b705202f63748136c2608ce80d2d5f20 Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Lanchon <lanchon@gmail.com>
* ARM: vfp: ensure that thread flushing works if preemptedRussell King2015-07-011-10/+13
| | | | | | | | | | | Prevent a preemption event causing the initialized VFP state being overwritten by ensuring that the VFP hardware access is disabled prior to starting initialization. We can then do this in safety while still allowing preemption to occur. Change-Id: I93922d95f641aa989b2acefe009a656e27d4d9bf Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Lanchon <lanchon@gmail.com>
* ARM: vfp: fix a hole in VFP thread migrationRussell King2015-07-013-55/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a hole in the VFP thread migration. Lets define two threads. Thread 1, we'll call 'interesting_thread' which is a thread which is running on CPU0, using VFP (so vfp_current_hw_state[0] = &interesting_thread->vfpstate) and gets migrated off to CPU1, where it continues execution of VFP instructions. Thread 2, we'll call 'new_cpu0_thread' which is the thread which takes over on CPU0. This has also been using VFP, and last used VFP on CPU0, but doesn't use it again. The following code will be executed twice: cpu = thread->cpu; /* * On SMP, if VFP is enabled, save the old state in * case the thread migrates to a different CPU. The * restoring is done lazily. */ if ((fpexc & FPEXC_EN) && vfp_current_hw_state[cpu]) { vfp_save_state(vfp_current_hw_state[cpu], fpexc); vfp_current_hw_state[cpu]->hard.cpu = cpu; } /* * Thread migration, just force the reloading of the * state on the new CPU in case the VFP registers * contain stale data. */ if (thread->vfpstate.hard.cpu != cpu) vfp_current_hw_state[cpu] = NULL; The first execution will be on CPU0 to switch away from 'interesting_thread'. interesting_thread->cpu will be 0. So, vfp_current_hw_state[0] points at interesting_thread->vfpstate. The hardware state will be saved, along with the CPU number (0) that it was executing on. 'thread' will be 'new_cpu0_thread' with new_cpu0_thread->cpu = 0. Also, because it was executing on CPU0, new_cpu0_thread->vfpstate.hard.cpu = 0, and so the thread migration check is not triggered. This means that vfp_current_hw_state[0] remains pointing at interesting_thread. The second execution will be on CPU1 to switch _to_ 'interesting_thread'. So, 'thread' will be 'interesting_thread' and interesting_thread->cpu now will be 1. The previous thread executing on CPU1 is not relevant to this so we shall ignore that. We get to the thread migration check. Here, we discover that interesting_thread->vfpstate.hard.cpu = 0, yet interesting_thread->cpu is now 1, indicating thread migration. We set vfp_current_hw_state[1] to NULL. So, at this point vfp_current_hw_state[] contains the following: [0] = &interesting_thread->vfpstate [1] = NULL Our interesting thread now executes a VFP instruction, takes a fault which loads the state into the VFP hardware. Now, through the assembly we now have: [0] = &interesting_thread->vfpstate [1] = &interesting_thread->vfpstate CPU1 stops due to ptrace (and so saves its VFP state) using the thread switch code above), and CPU0 calls vfp_sync_hwstate(). if (vfp_current_hw_state[cpu] == &thread->vfpstate) { vfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN); BANG, we corrupt interesting_thread's VFP state by overwriting the more up-to-date state saved by CPU1 with the old VFP state from CPU0. Fix this by ensuring that we have sane semantics for the various state describing variables: 1. vfp_current_hw_state[] points to the current owner of the context information stored in each CPUs hardware, or NULL if that state information is invalid. 2. thread->vfpstate.hard.cpu always contains the most recent CPU number which the state was loaded into or NR_CPUS if no CPU owns the state. So, for a particular CPU to be a valid owner of the VFP state for a particular thread t, two things must be true: vfp_current_hw_state[cpu] == &t->vfpstate && t->vfpstate.hard.cpu == cpu. and that is valid from the moment a CPU loads the saved VFP context into the hardware. This gives clear and consistent semantics to interpreting these variables. This patch also fixes thread copying, ensuring that t->vfpstate.hard.cpu is invalidated, otherwise CPU0 may believe it was the last owner. The hole can happen thus: - thread1 runs on CPU2 using VFP, migrates to CPU3, exits and thread_info freed. - New thread allocated from a previously running thread on CPU2, reusing memory for thread1 and copying vfp.hard.cpu. At this point, the following are true: new_thread1->vfpstate.hard.cpu == 2 &new_thread1->vfpstate == vfp_current_hw_state[2] Lastly, this also addresses thread flushing in a similar way to thread copying. Hole is: - thread runs on CPU0, using VFP, migrates to CPU1 but does not use VFP. - thread calls execve(), so thread flush happens, leaving vfp_current_hw_state[0] intact. This vfpstate is memset to 0 causing thread->vfpstate.hard.cpu = 0. - thread migrates back to CPU0 before using VFP. At this point, the following are true: thread->vfpstate.hard.cpu == 0 &thread->vfpstate == vfp_current_hw_state[0] Change-Id: Ifd268aa2499217ad0abd25cb0905b80bc5057229 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Lanchon <lanchon@gmail.com>
* n5120: set selinux to enforcingRGIB2015-05-151-1/+1
| | | | Change-Id: Ibc204aae682f175922d1886f93a7c3534c5d5692
* smdk4412: update mdm from KK sourcesbrissen2015-03-277-121/+364
| | | | Change-Id: If01d4a165b4b6bdc26a20fb449104e7bcb0c9403
* arm/crypto: Add optimized AES and SHA1 routinesHoward Su2014-12-266-0/+1882
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add assembler versions of AES and SHA1 for ARM platforms. This has provided up to a 50% improvement in IPsec/TCP throughout for tunnels using AES128/SHA1. Platform CPU SPeed Endian Before (bps) After (bps) Improvement IXP425 533 MHz big 11217042 15566294 ~38% KS8695 166 MHz little 3828549 5795373 ~51% Signed-off-by: David McCullough <ucdevel@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> ARM: 7626/1: arm/crypto: Make asm SHA-1 and AES code Thumb-2 compatible This patch fixes aes-armv4.S and sha1-armv4-large.S to work natively in Thumb. This allows ARM/Thumb interworking workarounds to be removed. I also take the opportunity to convert some explicit assembler directives for exported functions to the standard ENTRY()/ENDPROC(). For the code itself: * In sha1_block_data_order, use of TEQ with sp is deprecated in ARMv7 and not supported in Thumb. For the branches back to .L_00_15 and .L_40_59, the TEQ is converted to a CMP, under the assumption that clobbering the C flag here will not cause incorrect behaviour. For the first branch back to .L_20_39_or_60_79 the C flag is important, so sp is moved temporarily into another register so that TEQ can be used for the comparison. * In the AES code, most forms of register-indexed addressing with shifts and rotates are not permitted for loads and stores in Thumb, so the address calculation is done using a separate instruction for the Thumb case. The resulting code is unlikely to be optimally scheduled, but it should not have a large impact given the overall size of the code. I haven't run any benchmarks. Signed-off-by: Dave Martin <dave.martin@linaro.org> Tested-by: David McCullough <ucdevel@gmail.com> (ARM only) Acked-by: David McCullough <ucdevel@gmail.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> ARM: 7723/1: crypto: sha1-armv4-large.S: fix SP handling Make the SHA1 asm code ABI conformant by making sure all stack accesses occur above the stack pointer. Origin: http://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=1a9d60d2 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Cc: stable@vger.kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> ARM: 7837/3: fix Thumb-2 bug in AES assembler code commit 40190c85f427dcfdbab5dbef4ffd2510d649da1f upstream. Patch 638591c enabled building the AES assembler code in Thumb2 mode. However, this code used arithmetic involving PC rather than adr{l} instructions to generate PC-relative references to the lookup tables, and this needs to take into account the different PC offset when running in Thumb mode. Change-Id: I0d036eaa94dabefa0a025d522f415c663d00ae9f Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* n7100: Enable IDLETIMER which is used in netd.Howard Su2014-12-101-1/+1
| | | | Change-Id: Ie15e742139768865672990ba29757105447076ad
* ARM: 7670/1: fix the memset fixNicolas Pitre2014-11-241-20/+13
| | | | | | | | | | | | | | | | | | | | | | Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) optimizations") attempted to fix a compliance issue with the memset return value. However the memset itself became broken by that patch for misaligned pointers. This fixes the above by branching over the entry code from the misaligned fixup code to avoid reloading the original pointer. Also, because the function entry alignment is wrong in the Thumb mode compilation, that fixup code is moved to the end. While at it, the entry instructions are slightly reworked to help dual issue pipelines. Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Alexander Holler <holler@ahsoftware.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Change-Id: Ifdc6b0167104b42d23a72ffe5e6173f6e14c97ee
* ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) ↵Ivan Djelic2014-11-241-41/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | optimizations Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on assumptions about the implementation of memset and similar functions. The current ARM optimized memset code does not return the value of its first argument, as is usually expected from standard implementations. For instance in the following function: void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter) { memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter)); waiter->magic = waiter; INIT_LIST_HEAD(&waiter->list); } compiled as: 800554d0 <debug_mutex_lock_common>: 800554d0: e92d4008 push {r3, lr} 800554d4: e1a00001 mov r0, r1 800554d8: e3a02010 mov r2, #16 ; 0x10 800554dc: e3a01011 mov r1, #17 ; 0x11 800554e0: eb04426e bl 80165ea0 <memset> 800554e4: e1a03000 mov r3, r0 800554e8: e583000c str r0, [r3, #12] 800554ec: e5830000 str r0, [r3] 800554f0: e5830004 str r0, [r3, #4] 800554f4: e8bd8008 pop {r3, pc} GCC assumes memset returns the value of pointer 'waiter' in register r0; causing register/memory corruptions. This patch fixes the return value of the assembly version of memset. It adds a 'mov' instruction and merges an additional load+store into existing load/store instructions. For ease of review, here is a breakdown of the patch into 4 simple steps: Step 1 ====== Perform the following substitutions: ip -> r8, then r0 -> ip, and insert 'mov ip, r0' as the first statement of the function. At this point, we have a memset() implementation returning the proper result, but corrupting r8 on some paths (the ones that were using ip). Step 2 ====== Make sure r8 is saved and restored when (! CALGN(1)+0) == 1: save r8: - str lr, [sp, #-4]! + stmfd sp!, {r8, lr} and restore r8 on both exit paths: - ldmeqfd sp!, {pc} @ Now <64 bytes to go. + ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go. (...) tst r2, #16 stmneia ip!, {r1, r3, r8, lr} - ldr lr, [sp], #4 + ldmfd sp!, {r8, lr} Step 3 ====== Make sure r8 is saved and restored when (! CALGN(1)+0) == 0: save r8: - stmfd sp!, {r4-r7, lr} + stmfd sp!, {r4-r8, lr} and restore r8 on both exit paths: bgt 3b - ldmeqfd sp!, {r4-r7, pc} + ldmeqfd sp!, {r4-r8, pc} (...) tst r2, #16 stmneia ip!, {r4-r7} - ldmfd sp!, {r4-r7, lr} + ldmfd sp!, {r4-r8, lr} Step 4 ====== Rewrite register list "r4-r7, r8" as "r4-r8". Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Change-Id: Ie0c05696ed7c2e0d0a934233947e6a4b935e3405
* Fix kernel build errors for GT-N7000huangyuxuan012014-08-281-16/+10
| | | | | | | | | defconfig: cyanogenmod_n7000_defconfig Fix two mali400 drivers compile together Use mali400 r3p2 driver,disabled mali r3p1 driver. Change-Id: Ia6c4290414b3f97f57b38da41dae6107c4d9c657
* cpuidle-exynos4: calm down some logspamDan Pasanen2014-08-161-2/+2
| | | | | | | * noticed these CONSTANTLY flooding the log with screen off using wireless adb (so it was unplugged) Change-Id: I4df4f0da9f62cfd86552b77c71d4a2de11dac5d4
* d710: enable r3p1 mali drivers and autoregen defconfigDorian Snyder2014-08-041-9/+39
| | | | Change-Id: I08dc1617e3f77b63a4eee45f78abbb989a5276f4
* mach-exynos: cpufreq: Show list of available frequenciesDonggeun Kim2014-07-231-1/+22
| | | | | | | This patch enables 'scaling_available_frequencies' attribute showing list of available frequencies. Change-Id: I9b6ad786ffaaba8ad6fe5aa9045fd793c095b5ae
* smdk4412: initial support for n5120sbrissen2014-02-057-8/+3539
| | | | Change-Id: I21144c9f3146c9043b137f180c064627ebeed71e
* Fix light sensors for GT-N5100Truong Ta Xuan2014-01-171-2/+2
| | | | Change-Id: Ifd1bd76ec2ebf8014107747474145d0bfc9a3281
* sound-soc: fix muted headset mic after button pressffolkes2013-12-141-7/+1
| | | | | | | | this corrects a bug where after pressing the button on a headset the mic becomes muted. partial commit of "sound-soc: Sound platform and WM1811 changes" by SamsungOSRC Change-Id: I3593e7f0d19b4450d8a3ec55debaede4f80e01c0
* i9305/t0ltecdma: prevent freeze on smart dock plugmcampbellsmith2013-12-132-2/+2
| | | | Change-Id: If1db8d46c3547b807eb3d4ca1fe739b7b932ffb9
* Kone: add uhidsbrissen2013-12-112-0/+2
| | | | Change-Id: I920dfbfea63e07bde185c36d6b555a18f7a37747
* Merge "defconfig: patch other devices" into cm-11.0Daniel Hillenbrand2013-12-1013-212/+117
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| * defconfig: patch other devicesClément G2013-12-1013-212/+117
| | | | | | | | Change-Id: I2b0af5e9b52ac0aba26628b67d06f2a9453ba2b8
* | mali: bulk import of r3p2-01rel3 drivers from i9300-update12mcampbellsmith2013-12-101-1/+1
|/ | | | | | Courtesy of a similar commit from OMNI ROM. Requires updated mali blobs Change-Id: I9ee55b653b57b7c390f8e0e8cd4fc068f1c751c3
* Samsung i9300 Update 11sakindia1232013-12-099-13/+282
| | | | Change-Id: I7f6dbdd97e3ed66634bf123d43224a79524c04e9
* Add support for Note 8 (N5100 and N5110)sbrissen2013-11-1130-32/+14336
| | | | Change-Id: I6c9798682f9f6349b37cb452353bd0c0e6958401
* t0lte: prevent freeze on smart dock plugTanguy Pruvot2013-10-201-1/+1
| | | | | | | | Bug https://jira.cyanogenmod.org/browse/CYAN-2419 Could be applied on GT-I9305 and N7100 after tests. Change-Id: I9bd094f0f672fa67c7a36ec52e1133afe6b06c8d
* arm: mach-exynos: fix gps for n8000 and n801x devices definatelyHumberto Borba2013-09-234-4/+14
| | | | | Signed-off-by: Humberto Borba <humberos@gmail.com> Change-Id: I73e4f237c5cf67643f96930b3862155966bbf8bc
* Revert "max77693: Standardize the output of the "online" property"Ricardo Cerqueira2013-09-191-1/+1
| | | | | | | | This reverts commit 1a05356029493b29f866cf04f7550243ef3ae687, the enumerator breakage introduced by change Iafbd9fb45253b02d539ac0ba114f57b3bf9eeed4 can be reverted cleanly without further impact and it's a cleaner fix Change-Id: I351c320f98691241fbe321a0b1ac54152802deb4
* d710: cypress: fix home button and auto-update defconfigDorian Snyder2013-09-011-0/+3
| | | | Change-Id: I1dd142d0b168101a8170e742d115bf70a47daa48
* fix i925 compilingsbrissen2013-08-161-4/+3
| | | | Change-Id: I20678ad210403fc0cbb894fe16ba0edc357020b4
* cm exynos: enable selinux supportDaniel Hillenbrand2013-07-1312-90/+400
| | | | Change-Id: I90ed70f2071c5328d71a18e6cbd0cb8a8cc0c82d
* Fix GPS for n80xx devicesAndrew Dodd2013-07-051-2/+2
| | | | | | | | | | | | | | Why the hell does Samsung keep on derping the Makefile for GPS on n80xx devices? I'm getting tired of fixing this crap over and over again. Before they assumed wifi N80xx units didn't have GPS. Now they're keying compilation of the GPS stuff off of a nonexistent config entry. grr Change-Id: I034c521e6f398aa0d5f3a4fa1bb97e30e401a807
* smdk4412: add i925/p4noteltevzw supportsbrissen2013-06-2517-34/+3725
| | | | Change-Id: I17d3befd6a6538c16db0675253927068a09085c6
* d710: initial support for the Epic 4G Touch (SPH-D710)Dorian Snyder2013-06-2012-16/+3546
| | | | Change-Id: Iafbd9fb45253b02d539ac0ba114f57b3bf9eeed4
* smdk4412: Fix typoTamas Toth2013-06-181-1/+1
| | | | Change-Id: I9ab2dd10866b3b68cf86fbee9f95c130dc664192
* smdk4412: bulk update from i9300 update 9Daniel Hillenbrand2013-06-042-18/+11
| | | | Change-Id: Icd3e7b601f3f4c8b3dcf053fed5819fb7caf5296
* enable nfs supportDaniel Hillenbrand2013-06-018-14/+110
| | | | Change-Id: I84dc53e949be90ca464cb80432105130d089dd90
* 4412: builtin md4 and dnsresolverDaniel Hillenbrand2013-06-017-10/+10
| | | | Change-Id: Iab4e05f831e09d6cb2b40a2117accdb5b903a6b2
* i777, i9100, n7000: enable utf8 support for nlsDaniel Hillenbrand2013-06-013-3/+3
| | | | Change-Id: Iefbeee4aa149eaf9a5aca1651cc39a592f0e4208
* mach-u1: Improve touch sensitivity for MXT224E controllersakindia1232013-05-261-2/+2
| | | | | | | This reduces the janky scrolling observed Picked from : https://github.com/kgp700/exyroid-sgs2-jb/commit/2476a919c24f07e04f50a80442fc65d27af51ff5 Change-Id: I07c166f6f07b2874fa20be6f41bc5a016d93e653
* makefile: mach-exynos: Separate 4x10 and 4x12 objectssakindia1232013-05-261-2/+8
| | | | Change-Id: If3270ba8e454d224d18202ff5e751fc61792b4d7
* i777, i9100, n7000: regenerate defconfigsDaniel Hillenbrand2013-05-253-66/+42
| | | | Change-Id: Ibf954e20e70c9e6dac75b8e1da02bf5a1152098c
* u1: import from CyanogenMod/android_kernel_samsung_smdk4210Daniel Hillenbrand2013-05-2510-8/+10211
| | | | Change-Id: I9629a4060538c9c4c6a43a86a56826cd7123d1b5
* Correct md5sum executable on OSX hostsJavier Ferrer2013-05-032-2/+19
| | | | | | On OSX hosts the md5sum executable is called md5 instead. Change-Id: I0b8e3ab137136be6e45fd4b9f77f2c036e8b981a
generated by cgit v1.1 at 2024-06-08 09:30:00 +0000