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* dmaengine/ste_dma40: fix introduced warningsPhilippe Langlais2011-05-091-1/+1
| | | | | | | | | The compiler nowadays moans about possibly non-assigned variable. Fix this by default-assigning 0. Signed-off-by: Philippe Langlais <philippe.langlais@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: at_hdmac: specialize AHB interfaces to optimize transfersNicolas Ferre2011-05-022-11/+19
| | | | | | | | | | | DMA controller has two AHB interfaces on the SOC internal matrix. It is more efficient to specialize each interface as the access to memory can introduce latencies that are not compatible with peripheral accesses requirements. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: at_hdmac: remove channel status testing in taskletNicolas Ferre2011-05-021-7/+0
| | | | | | | | | | There is no need to test if channel is enabled in tasklet: - in error path, channel is disabled in interrupt routine - in normal path, this test is performed in sub functions to report a misuse of the engine. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: at_hdmac: debug information sg_len for prep_slave_sgNicolas Ferre2011-05-021-1/+2
| | | | | Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: at_hdmac: add cyclic DMA operation supportNicolas Ferre2011-05-022-16/+229
| | | | | Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: at_hdmac: modify way to use interruptsNicolas Ferre2011-05-022-5/+10
| | | | | | | | | | | Now we use Buffer Transfer Completed interrupts. If we want a chained buffer completed information, we setup the ATC_IEN bit in CTRLB register in the lli. This is done by set_desc_eol() function and used by memcpy/slave_sg functions. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* drivers, pch_dma: Fix uninitialized var before useLiu Yuan2011-04-061-1/+1
| | | | | | | | In the function pdc_desc_get(), var 'i' is not initialized before use. This patch fixes it. Signed-off-by: Liu Yuan <tailai.ly@taobao.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* Merge branch 'old_next' into nextVinod Koul2011-04-065-14/+28
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| * intel_mid_dma: fix runtime pm issuesKristen Carlson Accardi2011-04-011-4/+13
| | | | | | | | | | | | | | | | | | Use the correct api in probe to enable runtime pm for this driver. Additionally, do not just call legacy suspend for runtime_suspend, as this duplicates some work the pci core does for you. Signed-off-by: Kristen Carlson Accardi <kristen@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dma: use BUG_ON correctly in ppc4xx/adam.c, v4Coly Li2011-03-311-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes BUG_ON() usage correct in drivers/dma/ppc4xx/adam.c Cc: Vinod Koul <vinod.koul@intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Anatolij Gustschin <agust@denx.de> Cc: Sean MacLennan <smaclennan@pikatech.com> Cc: Joe Perches <joe@perches.com> Signed-off-by: Coly Li <bosong.ly@taobao.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dma: use BUG_ON correctly in mv_xor.c, v4Coly Li2011-03-311-3/+3
| | | | | | | | | | | | | | | | | | This patch makes BUG_ON() usage correct in drivers/dma/mv_xor.c Cc: Vinod Koul <vinod.koul@intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Coly Li <bosong.ly@taobao.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dma: use BUG_ON correctly in iop-adma.c, v4Coly Li2011-03-311-3/+3
| | | | | | | | | | | | | | | | | | This patch makes BUG_ON() usage correct in drivers/dma/iop-adma.c. Cc: Dan Williams <dan.j.williams@intel.com> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Coly Li <bosong.ly@taobao.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine/dw_dmac fix: dwc_scan_descriptors must compare first desc address ↵Viresh Kumar2011-03-311-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | also with llp dwc_scan_descriptors scans all descriptors from active_list in case transfer is not completed. It compares first_desc->lli.llp, and then all childrens of its tx_list. But it doesn't compare its own address, i.e. first_desc->txd.phys, as this is what we have initially programmed into the controller register. So this causes dma to stop and finish a transfer, which was never started. And thus fail. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | Merge branch 'irq-cleanup-for-linus' of ↵Linus Torvalds2011-03-271-29/+29
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: tile: Use generic show_interupts() tile: Convert to new irq function names dma: Ipu: Convert interupt code
| * | dma: Ipu: Convert interupt codeThomas Gleixner2011-03-251-29/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert to the new irq chip functions and cleanup the name space. [ Guennadi reported: irq_data_get_chip_data is undefined. Yes, I screwed up. it needs to be irq_data_get_irq_chip_data ] Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Dan Williams <dan.j.williams@intel.com> LKML-Reference: <alpine.LFD.2.00.1103251220000.31464@localhost6.localdomain6>
* | | mfd: mfd_cell is now implicitly available to timberdale driversAndres Salomon2011-03-231-1/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | The cell's platform_data is now accessed with a helper function; change clients to use that, and remove the now-unused data_size. Note that the mfd's platform_data is marked __devinitdata. This is still correct in all cases except for the timbgpio driver, whose remove hook has been changed to no longer reference the pdata. Signed-off-by: Andres Salomon <dilinger@queued.net> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
* | Merge branch 'next' of ↵Linus Torvalds2011-03-2212-1242/+1902
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (66 commits) avr32: at32ap700x: fix typo in DMA master configuration dmaengine/dmatest: Pass timeout via module params dma: let IMX_DMA depend on IMX_HAVE_DMA_V1 instead of an explicit list of SoCs fsldma: make halt behave nicely on all supported controllers fsldma: reduce locking during descriptor cleanup fsldma: support async_tx dependencies and automatic unmapping fsldma: fix controller lockups fsldma: minor codingstyle and consistency fixes fsldma: improve link descriptor debugging fsldma: use channel name in printk output fsldma: move related helper functions near each other dmatest: fix automatic buffer unmap type drivers, pch_dma: Fix warning when CONFIG_PM=n. dmaengine/dw_dmac fix: use readl & writel instead of __raw_readl & __raw_writel avr32: at32ap700x: Specify DMA Flow Controller, Src and Dst msize dw_dmac: Setting Default Burst length for transfers as 16. dw_dmac: Allow src/dst msize & flow controller to be configured at runtime dw_dmac: Changing type of src_master and dest_master to u8. dw_dmac: Pass Channel Priority from platform_data dw_dmac: Pass Channel Allocation Order from platform_data ...
| * dmaengine/dmatest: Pass timeout via module paramsViresh Kumar2011-03-221-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | When we try to test all channels present on our controller together, some channels of lower priority may be very slow as compared to others. If number of transfers is unlimited, some channels may timeout and will not finish within 3 seconds. Thus, while doing such regress testing we may need to have higher value of timeouts. This patch adds support for passing timeout value via module parameters. Default value is 3 msec, a negative value means max timeout possible. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dma: let IMX_DMA depend on IMX_HAVE_DMA_V1 instead of an explicit list of SoCsUwe Kleine-König2011-03-221-1/+1
| | | | | | | | | | | | | | | | As a side effect this makes IMX_DMA selectable on i.MX21 again, because the symbol ARCH_MX21 doesn't exist (MACH_MX21 would have been more correct). Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: make halt behave nicely on all supported controllersIra Snyder2011-03-111-3/+16
| | | | | | | | | | | | | | | | | | | | The original dma_halt() function set the CA (channel abort) bit on both the 83xx and 85xx controllers. This is incorrect on the 83xx, where this bit means TEM (transfer error mask) instead. The 83xx doesn't support channel abort, so we only do this operation on 85xx. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: reduce locking during descriptor cleanupIra Snyder2011-03-111-62/+46
| | | | | | | | | | | | | | | | | | | | | | This merges the fsl_chan_ld_cleanup() function into the dma_do_tasklet() function to reduce locking overhead. In the best case, we will be able to keep the DMA controller busy while we are freeing used descriptors. In all cases, the spinlock is grabbed two times fewer than before on each transaction. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: support async_tx dependencies and automatic unmappingIra Snyder2011-03-111-36/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous to this patch, the dma_run_dependencies() function has been called while holding desc_lock. This function can call tx_submit() for other descriptors, which may try to re-grab the lock. Avoid this by moving the descriptors to be cleaned up to a temporary list, and dropping the lock before cleanup. At the same time, add support for automatic unmapping of src and dst buffers, as offered by the DMAEngine API. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: fix controller lockupsIra Snyder2011-03-112-122/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling poisoning in the dmapool API quickly showed that the DMA controller was fetching descriptors that should not have been in use. This has caused intermittent controller lockups during testing. I have been unable to figure out the exact set of conditions which cause this to happen. However, I believe it is related to the driver using the hardware registers to track whether the controller is busy or not. The code can incorrectly decide that the hardware is idle due to lag between register writes and the hardware actually becoming busy. To fix this, the driver has been reworked to explicitly track the state of the hardware, rather than try to guess what it is doing based on the register values. This has passed dmatest with 10 threads per channel, 100000 iterations per thread several times without error. Previously, this would fail within a few seconds. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: minor codingstyle and consistency fixesIra Snyder2011-03-112-18/+15
| | | | | | | | | | | | | | | | | | This fixes some minor violations of the coding style. It also changes the style of the device_prep_dma_*() function definitions so they are identical. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: improve link descriptor debuggingIra Snyder2011-03-111-6/+15
| | | | | | | | | | | | | | | | This adds better tracking to link descriptor allocations, callbacks, and frees. This makes it much easier to track errors with link descriptors. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: use channel name in printk outputIra Snyder2011-03-112-34/+36
| | | | | | | | | | | | | | | | | | This makes debugging the driver much easier when multiple channels are running concurrently. In addition, you can see how much descriptor memory each channel has allocated via the dmapool API in sysfs. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: move related helper functions near each otherIra Snyder2011-03-111-52/+64
| | | | | | | | | | | | | | | | This is a purely cosmetic cleanup. It is nice to have related functions right next to each other in the code. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dmatest: fix automatic buffer unmap typeIra Snyder2011-03-111-1/+6
| | | | | | | | | | | | | | | | | | The dmatest code relies on the DMAEngine API to automatically call dma_unmap_single() on src buffers. The flags it passes are incorrect, fix them. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * drivers, pch_dma: Fix warning when CONFIG_PM=n.Rakib Mullick2011-03-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_PM=n, we get the following warning: drivers/dma/pch_dma.c:741: warning: ‘pch_dma_suspend’ defined but not used drivers/dma/pch_dma.c:755: warning: ‘pch_dma_resume’ defined but not used To fix it, wrap pch_dma_{suspend,resume} and pch_dma_{save,restore}_regs functions with CONFIG_PM. Signed-off-by: Rakib Mullick <rakib.mullick@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine/dw_dmac fix: use readl & writel instead of __raw_readl & __raw_writelViresh Kumar2011-03-071-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARMv7 cores, device memory mapped as Normal Non-cacheable, may not guarantee ordered access causing failures in device drivers that do not use the mandatory memory barriers. readl & writel versions contain necessary memory barriers for this. commit 79f64dbf68c8a9779a7e9a25e0a9f0217a25b57a: "ARM: 6273/1: Add barriers to the I/O accessors if ARM_DMA_MEM_BUFFERABLE" can be referred for more information on this. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dw_dmac: Setting Default Burst length for transfers as 16.Viresh Kumar2011-03-071-2/+2
| | | | | | | | | | | | | | | | This patch sets default Burst length for all transfer to 16. This will enhance performance when user doesn't have any chan->private data. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dw_dmac: Allow src/dst msize & flow controller to be configured at runtimeViresh KUMAR2011-03-072-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Msize or Burst Size is peripheral dependent in case of prep_slave_sg and cyclic_prep transfers, and in case of memcpy transfers it is platform dependent. So msize configuration must come from platform data. Also some peripherals (ex: JPEG), need to be flow controller for dma transfers, so this information in case of slave_sg & cyclic_prep transfers must come from platform data. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dw_dmac: Pass Channel Priority from platform_dataViresh Kumar2011-03-072-1/+13
| | | | | | | | | | | | | | | | | | | | In Synopsys designware, channel priority is programmable. This patch adds support for passing channel priority through platform data. By default Ascending channel priority will be followed, i.e. channel 0 will get highest priority and channel 7 will get lowest. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dw_dmac: Pass Channel Allocation Order from platform_dataViresh Kumar2011-03-071-1/+5
| | | | | | | | | | | | | | | | | | | | In SPEAr Platform channels 4-7 have more Fifo depth. So we must get better channel first. This patch introduces concept of channel allocation order in dw_dmac. If user doesn't pass anything or 0, than normal (ascending) channel allocation will follow, else channels will be allocated in descending order. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dw_dmac: Mark all tx_descriptors with DMA_CRTL_ACK after xfer finishViresh Kumar2011-03-071-0/+7
| | | | | | | | | | | | | | | | | | | | dwc_desc_get checks all descriptors for DMA_CTRL_ACK before allocating them for transfers. And descriptors are not marked with DMA_CRTL_ACK after transfer finishes. Thus descriptor once used is not usable again. This patch marks descriptors with DMA_CRTL_ACK after dma xfer finishes Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dw_dmac: Change value of DWC_MAX_COUNT to 4095.Viresh Kumar2011-03-071-3/+2
| | | | | | | | | | | | | | | | Every descriptor can transfer a maximum count of 4095 (12 bits, in control reg), So we must have DWC_MAX_COUNT as 4095 instead of 2048. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dw_dmac: Adding support for 64 bit access width for memcpy xfersViresh Kumar2011-03-071-1/+3
| | | | | | | | | | Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dw_dmac: Calling dwc_scan_descriptors from dwc_tx_status() after taking lockViresh Kumar2011-03-071-0/+2
| | | | | | | | | | | | | | | | | | | | Lock must be taken before calling dwc_scan_descriptors, as this may access/modify shared data and queues. dwc_tx_status wasn't taking lock before calling this routine. This patch add code that takes lock before calling dwc_scan_descriptors. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dw_dmac: Move single descriptor from dwc->queue to dwc->active_list in ↵Viresh Kumar2011-03-071-12/+8
| | | | | | | | | | | | | | | | | | | | | | dwc_complete_all dwc_complete_all and other routines was removing all descriptors from dwc->queue and pushing them to dwc->active_list. Only one was required to be removed. Also we are calling dwc_dostart, once list is fixed. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dw_dmac: Replace module_init() with subsys_initcall()Viresh Kumar2011-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | In some cases users of dw_dmac are initialized before dw_dmac, and if they try to use dw_dmac, they simply fail. So its better we register init() routine of driver using subsys_initcall() instead of module_init(), so that dma driver is available at the earliest possible. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dw_dmac: Remove compilation dependency from AVR32 and put on HAVE_CLKViresh Kumar2011-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This driver will now be used in atleast two platforms AVR32 & ARM. And there is no actual hardware dependency of this driver over AVR32 or ARM. So this dependency can be removed altogether. Also dw_dmac driver uses clk framework and must have compilation dependency on HAVE_CLK Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: mxs-dma: add dma support for i.MX23/28Shawn Guo2011-03-023-0/+733
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds dma support for Freescale MXS-based SoC i.MX23/28, including apbh-dma and apbx-dma. * apbh-dma and apbx-dma are supported in the driver as two mxs-dma instances. * apbh-dma is different between mx23 and mx28, hardware version register is used to differentiate. * mxs-dma supports pio function besides data transfer. The driver uses dma_data_direction DMA_NONE to identify the pio mode, and steals sgl and sg_len to get pio words and numbers from clients. * mxs dmaengine has some very specific features, like sense function and the special NAND support (nand_lock, nand_wait4ready). These are too specific to implemented in generic dmaengine driver. * The driver refers to imx-sdma and only a single descriptor is statically assigned to each channel. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * pch_dma: set the number of array correctlyTomoya MORINAGA2011-02-261-2/+2
| | | | | | | | | | | | | | set the number of array correctly. Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * pch_dma: fix kernel error issueTomoya MORINAGA2011-02-261-15/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fix the following kernel error ------------[ cut here ]------------ WARNING: at kernel/softirq.c:159 _local_bh_enable_ip.clone.5+0x35/0x71() Hardware name: To be filled by O.E.M. Modules linked in: pch_uart pch_dma fuse mga drm cpufreq_ondemand acpi_cpufreq mperf ip6t_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 ip6table_filter ip6_tables ipv6 uinput snd_hda_codec_realtek snd_hda_intel snd_hda_codec matroxfb_base snd_hwdep 8250_pnp snd_seq snd_seq_device matroxfb_DAC1064 snd_pcm joydev 8250 matroxfb_accel snd_timer matroxfb_Ti3026 ppdev pegasus parport_pc snd parport matroxfb_g450 g450_pll serial_core video output matroxfb_misc soundcore snd_page_alloc serio_raw pcspkr ext4 jbd2 crc16 sdhci_pci sdhci mmc_core floppy [last unloaded: scsi_wait_scan] Pid: 0, comm: swapper Not tainted 2.6.37.upstream_check+ #8 Call Trace: [<c0433add>] warn_slowpath_common+0x65/0x7a [<c043825b>] ? _local_bh_enable_ip.clone.5+0x35/0x71 [<c0433b01>] warn_slowpath_null+0xf/0x13 [<c043825b>] _local_bh_enable_ip.clone.5+0x35/0x71 [<c043829f>] local_bh_enable_ip+0x8/0xa [<c06ec471>] _raw_spin_unlock_bh+0x10/0x12 [<f82b57dd>] pd_prep_slave_sg+0xba/0x200 [pch_dma] [<f82f7b7a>] pch_uart_interrupt+0x44d/0x6aa [pch_uart] [<c046fa97>] handle_IRQ_event+0x1d/0x9e [<c047146f>] handle_fasteoi_irq+0x90/0xc7 [<c04713df>] ? handle_fasteoi_irq+0x0/0xc7 <IRQ> [<c04045af>] ? do_IRQ+0x3e/0x89 [<c04035a9>] ? common_interrupt+0x29/0x30 [<c04400d8>] ? sys_getpriority+0x12d/0x1a2 [<c058bb2b>] ? arch_local_irq_enable+0x5/0xb [<c058c740>] ? acpi_idle_enter_bm+0x22a/0x261 [<c0648b11>] ? cpuidle_idle_call+0x70/0xa1 [<c0401f44>] ? cpu_idle+0x49/0x6a [<c06d9fc4>] ? rest_init+0x58/0x5a [<c089e762>] ? start_kernel+0x2d0/0x2d5 [<c089e0ce>] ? i386_start_kernel+0xce/0xd5 Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * Merge branch 'dw_dmac' into dmaengineDan Williams2011-02-141-14/+22
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| | * dmaengine/dw_dmac: provide a mechanism to indicate private devicesJamie Iles2011-01-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms (e.g. Picochip PC3XX) have multiple DMA controllers where some may be used for slave transfers and others for general purpose memcpy type transfers. Add a .is_private boolean to the platform data structure so that controllers can be marked as private so that the DMA_PRIVATE capability will be set for that controller. Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | * dmaengine/dw_dmac: allow src/dst masters to be configured at runtimeJamie Iles2011-01-291-14/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms have flexible mastering capabilities and this needs to be selected at runtime. If the platform has specified private data in the form of the dw_dma_slave then fetch the source and destination masters from here. If this isn't present, default to the previous of 0 and 1. v2: cleanup whitespace Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | * dmaengine/dw_dmac: don't scan descriptors if no xfers in progressJamie Iles2011-01-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some hardware (picoChip picoXCell in particular) sometimes has the block transfer complete bit being set for a channel after the whole transfer has completed. If we don't have any transfers in the active list then don't bother to scan the descriptors. This often happens in normal operation and doesn't require the channel to be reset. v2: cleanup whitespace Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | Merge branch 'dma40' into dmaengineDan Williams2011-02-143-928/+758
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| | * | dma40: cyclic xfer supportRabin Vincent2011-01-303-49/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support cyclic transfers, which are useful for ALSA drivers. Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
generated by cgit v1.1 at 2024-12-27 15:05:23 +0000