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* | PCI: aerdrv: rework aer_isr_one_error()Hidetoshi Seto2010-05-111-21/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Divide tricky for-loop into readable if-blocks. The logic to set multi_error_valid (to force walking pci bus hierarchy to find 2nd~ error devices) is changed too, to check MULTI_{,_UN}COR_RCV bit individually and to force walk only when it is required. And rework setting e_info->severity for uncorrectable, not to use magic numbers. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | PCI: aerdrv: rework add_error_deviceHidetoshi Seto2010-05-111-5/+13
| | | | | | | | | | | | | | | | Stop iteration if we cannot register any more. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | PCI: aerdrv: remove compare_device_idHidetoshi Seto2010-05-111-16/+2
| | | | | | | | | | | | | | | | Inline too-simple subroutine only used here. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | PCI: aerdrv: introduce is_error_sourceHidetoshi Seto2010-05-111-40/+34
| | | | | | | | | | | | | | | | | | | | Take core part of find_device_iter() to make a new function is_error_source() that checks given device has report an error or not. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | PCI: aerdrv: rework find_source_deviceHidetoshi Seto2010-05-111-12/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | Return bool to indicate that the source device is found or not. This allows us to skip calling aer_process_err_devices() if we can. And move dev_printk for debug into this function. v2: return bool instead of int Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | PCI: aerdrv: make aer_{en,dis}able_rootport staticHidetoshi Seto2010-05-113-109/+107
| | | | | | | | | | | | | | | | | | These functions are only called from init/remove path of aerdrv, so move them from aerdrv_core.c to aerdrv.c, to make them static. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | PCI: aerdrv: cleanup inconsistent functionsHidetoshi Seto2010-05-113-18/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This cleanup solves some minor naming issues by removing unuseful function aer_delete_rootport() and by renaming disable_root_aer() to aer_disable_rootport(). - Inconsistent location of alloc & free: The struct rpc is allocated in aer_alloc_rpc() at aerdrv.c while it is implicitly freed in aer_delete_rootport() at aerdrv_core.c. - Inconsistent function name: It makes a bit confusion that aer_delete_rootport() is seemed to be paired with aer_enable_rootport(), i.e. there is neither "add" against "delete" nor "disable" against "enable". Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | PCI: aerdrv: RsvdP of PCI_ERR_ROOT_COMMANDHidetoshi Seto2010-05-112-11/+17
|/ | | | | | | | Handle preserved bits properly. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI aerdrv: use correct bit defines and add 2ms delay to aer_root_resetAlexander Duyck2010-04-081-2/+8
| | | | | | | | | | | | | | | | | While testing completion timeouts I found that hardware was not recovering. It looks like the hot reset was never being propagated to the endpoint devices on the bus due to the fact that we were clearing the bit too quickly. The documentation I have states that we should be transmitting hot reset TS1s for 2ms. To achieve this I have added a 2ms delay from the time we set the secondary bus reset bit to the time we clear it. In addition I changed the define used for the secondary bus reset bit to match the register define that was being used. Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* include cleanup: Update gfp.h and slab.h includes to prepare for breaking ↵Tejun Heo2010-03-305-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
* PM: Allow PCI devices to suspend/resume asynchronouslyRafael J. Wysocki2010-02-261-0/+1
| | | | | | | | | | | | | | Set power.async_suspend for all PCI devices and PCIe port services, so that they can be suspended and resumed in parallel with other devices they don't depend on in a known way (i.e. devices which are not their parents or children). This only affects the "regular" suspend and resume stages, which means in particular that the restoration of the PCI devices' standard configuration registers during resume will still be carried out synchronously (at the "early" resume stage). Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
* PCIe PME: use pci_pcie_cap()Kenji Kaneshige2010-02-221-4/+4
| | | | | | | | | Use pci_pcie_cap() instead of pci_find_capability() to get PCIe capability offset. This reduces redundant search in PCI configuration space. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCIe PME: use pci_is_pcie()Kenji Kaneshige2010-02-221-3/+3
| | | | | | | | Use pci_is_pcie() instead of looking at obsolete is_pcie field in struct pci_dev. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI PM: Make it possible to force using INTx for PCIe PME signalingRafael J. Wysocki2010-02-224-3/+67
| | | | | | | | | | | | | | | | | | | | | | Apparently, some machines may have problems with PCI run-time power management if MSIs are used for the native PCIe PME signaling. In particular, on the MSI Wind U-100 PCIe PME interrupts are not generated by a PCIe root port after a resume from suspend to RAM, if the system wake-up was triggered by a PME from the device attached to this port. [It doesn't help to free the interrupt on suspend and request it back on resume, even if that is done along with disabling the MSI and re-enabling it, respectively.] However, if INTx interrupts are used for this purpose on the same machine, everything works just fine. For this reason, add a kernel command line switch allowing one to request that MSIs be not used for the native PCIe PME signaling, introduce a DMI table allowing us to blacklist machines that need this switch to be set by default and put the MSI Wind U-100 into this table. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI PM: PCIe PME root port service driverRafael J. Wysocki2010-02-226-0/+589
| | | | | | | | | | | | | | | | | | | | | | | | | | PCIe native PME detection mechanism is based on interrupts generated by root ports or event collectors every time a PCIe device sends a PME message upstream. Once a PME message has been sent by an endpoint device and received by its root port (or event collector in the case of root complex integrated endpoints), the Requester ID from the message header is registered in the root port's Root Status register. At the same time, the PME Status bit of the Root Status register is set to indicate that there's a PME to handle. If PCIe PME interrupt is enabled for the root port, it generates an interrupt once the PME Status has been set. After receiving the interrupt, the kernel can identify the PCIe device that generated the PME using the Requester ID from the root port's Root Status register. [For details, see PCI Express Base Specification, Rev. 2.0.] Implement a driver for the PCIe PME root port service working in accordance with the above description. Based on a patch from Shaohua Li <shaohua.li@intel.com>. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: fix nested spinlock hang in aer_injectAndrew Patterson2010-01-251-6/+6
| | | | | | | | | | | | | | | | The aer_inject module hangs in aer_inject() when checking the device's error masks. The hang is due to a recursive use of the aer_inject lock. The aer_inject() routine grabs the lock while processing the error and then calls pci_read_config_dword to read the masks. The pci_read_config_dword routine is earlier overridden by pci_read_aer, which among other things, grabs the aer_inject lock. Fixed by moving the pci_read_config_dword calls to read the masks to before the lock is taken. Acked-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCIe AER: prevent AER injection if hardware masks error reportingYouquan,Song2010-01-041-1/+19
| | | | | | | | | | | | | | The Correcteable/Uncorrectable Error Mask Registers are used by PCIe AER driver which will controls the reporting of individual errors to PCIe RC via PCIe error messages. If hardware masks special error reporting to RC, the aer_inject driver should not inject aer error. Acked-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Youquan, Song <youquan.song@intel.com> Acked-by: Ying, Huang <ying.huang@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: AER: fix aer inject result in kernel oopsYouquan,Song2010-01-041-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the BIOS does not export _OSC to allow OS take over the PCIe AER, the pcie aer driver will not initialize the aer service. However, the aer_inject driver does not check this scenario, which results in a kernel oops when injecting an aer error into OS. For example: BUG: unable to handle kernel NULL pointer dereference at 0000000000000350 IP: [<ffffffff812e08f7>] _spin_lock_irqsave+0xc/0x23 PGD 155c41067 PUD 157fe0067 PMD 0 Oops: 0002 [#1] SMP Pid: 5119, comm: aer-inject Not tainted 2.6.32-rc8-mce #2 RIP: 0010:[<ffffffff812e08f7>] [<ffffffff812e08f7>] _spin_lock_irqsave+0xc/0x23 RSP: 0018:ffff880157f81e28 EFLAGS: 00010096 RAX: 0000000000000296 RBX: 0000000000000000 RCX: 0000000000000100 RDX: 0000000000010000 RSI: 0000000000000246 RDI: 0000000000000350 RBP: ffff880157f81e28 R08: 0000000000000004 R09: ffff880157f81dac R10: ffff88015a666f60 R11: ffff88015a666f40 R12: ffff88015758cc00 R13: 0000000000000350 R14: 0000000000000000 R15: 0000000000000100 FS: 00007f4d4a66e6f0(0000) GS:ffff8800282e0000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b CR2: 0000000000000350 CR3: 000000015661a000 CR4: 00000000000006e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 Process aer-inject (pid: 5119, threadinfo ffff880157f80000, task ffff8801585f4340) Stack: ffff880157f81e78 ffffffff811b1615 ffff880157f81e78 ffffffff81222823 Call Trace: [<ffffffff811b1615>] aer_irq+0x38/0x117 [<ffffffff81222823>] ? device_for_each_child+0x5f/0x6f [<ffffffffa00967bf>] aer_inject_write+0x409/0x45e [aer_inject] [<ffffffff810eb80e>] vfs_write+0xae/0x16a [<ffffffff810eb98e>] sys_write+0x47/0x6e [<ffffffff8100ba2b>] system_call_fastpath+0x16/0x1b RIP [<ffffffff812e08f7>] _spin_lock_irqsave+0xc/0x23 RSP <ffff880157f81e28> CR2: 0000000000000350 So check the _OSC before assuming that AER is available to the OS. Signed-off-by: Youquan, Song <youquan.song@intel.com> Acked-by: Ying, Huang <ying.huang@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: pcie portdrv: style cleanupHidetoshi Seto2010-01-042-18/+15
| | | | | | | | | | | | | | | | | | | No change in logic. Before: drivers/pci/pcie/portdrv_core.c: total: 7 errors, 2 warnings, 508 lines checked drivers/pci/pcie/portdrv_pci.c: total: 4 errors, 2 warnings, 300 lines checked After: drivers/pci/pcie/portdrv_core.c: total: 0 errors, 0 warnings, 506 lines checked drivers/pci/pcie/portdrv_pci.c: total: 0 errors, 0 warnings, 299 lines checked Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: change PCI nomenclature in drivers/pci/ (non-comment changes)Stefan Assmann2009-12-164-6/+6
| | | | | | | | | | | | Changing occurrences of variants of PCI-X and PCIe to the PCI-SIG terms listed in the "Trademark and Logo Usage Guidelines". http://www.pcisig.com/developers/procedures/logos/Trademark_and_Logo_Usage_Guidelines_updated_112206.pdf Patch is limited to drivers/pci/ and changes concern non-comment parts or anything that might be visible to the user. Signed-off-by: Stefan Assmann <sassmann@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: change PCI nomenclature in drivers/pci/ (comment changes)Stefan Assmann2009-12-165-9/+9
| | | | | | | | | | | Changing occurrences of variants of PCI-X and PCIe to the PCI-SIG terms listed in the "Trademark and Logo Usage Guidelines". http://www.pcisig.com/developers/procedures/logos/Trademark_and_Logo_Usage_Guidelines_updated_112206.pdf Patch is limited to drivers/pci/ and changes concern comments only. Signed-off-by: Stefan Assmann <sassmann@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* const: constify remaining dev_pm_opsAlexey Dobriyan2009-12-151-1/+1
| | | | | | Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* PCI: fix BUG_ON triggered by logical PCIe root port removalKenji Kaneshige2009-12-041-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This problem happened when removing PCIe root port using PCI logical hotplug operation. The immediate cause of this problem is that the pointer to invalid data structure is passed to pcie_update_aspm_capable() by pcie_aspm_exit_link_state(). When pcie_aspm_exit_link_state() received a pointer to root port link, it unconfigures the root port link and frees its data structure at first. At this point, there are not links to configure under the root port and the data structure for root port link is already freed. So pcie_aspm_exit_link_state() must not call pcie_update_aspm_capable() and pcie_config_aspm_path(). This patch fixes the problem by changing pcie_aspm_exit_link_state() not to call pcie_update_aspm_capable() and pcie_config_aspm_path() if the specified link is root port link. ------------[ cut here ]------------ kernel BUG at drivers/pci/pcie/aspm.c:606! invalid opcode: 0000 [#1] SMP DEBUG_PAGEALLOC last sysfs file: /sys/devices/pci0000:40/0000:40:13.0/remove CPU 1 Modules linked in: shpchp Pid: 9345, comm: sysfsd Not tainted 2.6.32-rc5 #98 ProLiant DL785 G6 RIP: 0010:[<ffffffff811df69b>] [<ffffffff811df69b>] pcie_update_aspm_capable+0x15/0xbe RSP: 0018:ffff88082a2f5ca0 EFLAGS: 00010202 RAX: 0000000000000e77 RBX: ffff88182cc3e000 RCX: ffff88082a33d006 RDX: 0000000000000001 RSI: ffffffff811dff4a RDI: ffff88182cc3e000 RBP: ffff88082a2f5cc0 R08: ffff88182cc3e000 R09: 0000000000000000 R10: ffff88182fc00180 R11: ffff88182fc00198 R12: ffff88182cc3e000 R13: 0000000000000000 R14: ffff88182cc3e000 R15: ffff88082a2f5e20 FS: 00007f259a64b6f0(0000) GS:ffff880864600000(0000) knlGS:0000000000000000 CS: 0010 DS: 0018 ES: 0018 CR0: 000000008005003b CR2: 00007feb53f73da0 CR3: 000000102cc94000 CR4: 00000000000006e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 Process sysfsd (pid: 9345, threadinfo ffff88082a2f4000, task ffff88082a33cf00) Stack: ffff88182cc3e000 ffff88182cc3e000 0000000000000000 ffff88082a33cf00 <0> ffff88082a2f5cf0 ffffffff811dff52 ffff88082a2f5cf0 ffff88082c525168 <0> ffff88402c9fd2f8 ffff88402c9fd2f8 ffff88082a2f5d20 ffffffff811d7db2 Call Trace: [<ffffffff811dff52>] pcie_aspm_exit_link_state+0xf5/0x11e [<ffffffff811d7db2>] pci_stop_bus_device+0x76/0x7e [<ffffffff811d7d67>] pci_stop_bus_device+0x2b/0x7e [<ffffffff811d7e4f>] pci_remove_bus_device+0x15/0xb9 [<ffffffff811dcb8c>] remove_callback+0x29/0x3a [<ffffffff81135aeb>] sysfs_schedule_callback_work+0x15/0x6d [<ffffffff81072790>] worker_thread+0x19d/0x298 [<ffffffff8107273b>] ? worker_thread+0x148/0x298 [<ffffffff81135ad6>] ? sysfs_schedule_callback_work+0x0/0x6d [<ffffffff810765c0>] ? autoremove_wake_function+0x0/0x38 [<ffffffff810725f3>] ? worker_thread+0x0/0x298 [<ffffffff8107629e>] kthread+0x7d/0x85 [<ffffffff8102eafa>] child_rip+0xa/0x20 [<ffffffff8102e4bc>] ? restore_args+0x0/0x30 [<ffffffff81076221>] ? kthread+0x0/0x85 [<ffffffff8102eaf0>] ? child_rip+0x0/0x20 Code: 89 e5 8a 50 48 31 c0 c0 ea 03 83 e2 07 e8 b2 de fe ff c9 48 98 c3 55 48 89 e5 41 56 49 89 fe 41 55 41 54 53 48 83 7f 10 00 74 04 <0f> 0b eb fe 48 8b 05 da 7d 63 00 4c 8d 60 e8 4c 89 e1 eb 24 4c RIP [<ffffffff811df69b>] pcie_update_aspm_capable+0x15/0xbe RSP <ffff88082a2f5ca0> ---[ end trace 6ae0f65bdeab8555 ]--- Reported-by: Alex Chiang <achiang@hp.com> Tested-by: Alex Chiang <achiang@hp.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: remove ifdefed pci_cleanup_aer_correct_error_statusAndrew Patterson2009-12-041-17/+0
| | | | | | | | The pci_cleanup_aer_correct_error_status() function has been #if 0'd out since 2.6.25. Time to remove the dead code. Signed-off-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: unconditionally clear AER uncorr status register during cleanupAndrew Patterson2009-12-041-7/+3
| | | | | | | | | | | | | | | | | | | | | The current implementation of pci_cleanup_aer_uncorrect_error_status only clears either fatal or non-fatal error status bits depending on the state of the I/O channel. This implementation will then often leave some bits set after PCI error recovery completes. The uncleared bit settings will then be falsely reported the next time an AER interrupt is generated for that hierarchy. An easy way to illustrate this issue is to use the aer-inject module to simultaneously inject both an uncorrectable non-fatal and uncorrectable fatal error. One of the errors will not be cleared. This patch resolves this issue by unconditionally clearing all bits in the AER uncorrectable status register. All settings and corrective action strategies are saved and determined before pci_cleanup_aer_uncorrect_error_status is called, so this change should not affect errory handling functionality. Signed-off-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: portdrv: remove redundant definitionsKenji Kaneshige2009-12-042-24/+9
| | | | | | | | Remove unnecessary definitions from portdrv.h and use generic definitions instead. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: portdrv: remove unnecessary struct pcie_port_dataKenji Kaneshige2009-12-044-26/+9
| | | | | | | | | | | | | | Remove 'port_type' field in struct pcie_port_data(), because we can get port type information from struct pci_dev. With this change, this patch also does followings: - Remove struct pcie_port_data because it no longer has any field. - Remove portdrv private definitions about port type (PCIE_RC_PORT, PCIE_SW_UPSTREAM_PORT and PCIE_SW_DOWNSTREAM_PORT), and use generic definitions instead. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: portdrv: minor cleanup for pcie_port_device_registerKenji Kaneshige2009-12-041-11/+10
| | | | | | | Minor cleanups for pcie_port_device_register(). Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: portdrv: add missing irq cleanupKenji Kaneshige2009-12-041-7/+12
| | | | | | | | Add missing service irqs cleanup in the error code path of pcie_port_device_register(). Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: portdrv: enable device before irq initializationKenji Kaneshige2009-12-041-10/+11
| | | | | | | | | Call pci_enable_device() before initializing service irqs, because legacy interrupt is initialized in pci_enable_device() on some architectures. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: portdrv: cleanup service irqs initializationKenji Kaneshige2009-12-041-42/+29
| | | | | | | | | | | | | | | | | | | This patch cleans up the service irqs initialization as follows: - Remove 'irq_mode' field in pcie_port_data and related definitions, which is not needed because we can get the same information from 'is_msix', 'is_msi' and 'pin' fields in struct pci_dev. - Change the name of 'vectors' argument of assign_interrupt_mode() to 'irqs' because it holds irq numbers actually. People might confuse it with CPU vector or MSI/MSI-X vector. - Change function name assign_interrupt_mode() to init_service_irqs() becasuse we no longer have 'irq_mode' data structure, and new name is more straightforward (IMO). Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: portdrv: check capabilities firstKenji Kaneshige2009-12-041-2/+4
| | | | | | | | Move capability check capability to the beginning of pcie_port_device_register() prevents redundant execution path. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: portdrv: move PME capability checkKenji Kaneshige2009-12-041-3/+3
| | | | | | | | No reason to check PME capability outside get_port_device_capability(). Do it in get_port_device_capability(). Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: portdrv: remove redundant pcie type calculationKenji Kaneshige2009-12-041-6/+2
| | | | | | | | PCIe port type is already stored in 'pcie_type' field of struct pci_dev. So we don't need to get it from pci configuration space. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: portdrv: cleanup pcie_device registrationKenji Kaneshige2009-12-041-51/+26
| | | | | | | | | In the current port bus driver implementation, pcie_device allocation, initialization and registration are done in separated functions. Doing those in one function make the code simple and easier to read. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: portdrv: remove redundant pcie_port_device_probeKenji Kaneshige2009-12-043-29/+8
| | | | | | | | | We don't need pcie_port_device_probe() because we can get pci device/port type using pci_is_pcie() and 'pcie_type' fields in struct pci_dev. Remove pcie_port_device_probe(). Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCIe AER: use pci_is_pcie()Kenji Kaneshige2009-11-242-3/+3
| | | | | | | | Changes for PCIe AER driver to use pci_is_pcie() instead of checking pci_dev->is_pcie. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCIe ASPM: use pci_is_pcie()Kenji Kaneshige2009-11-241-9/+12
| | | | | | | | Change for PCIe ASPM driver to use pci_is_pcie() instead of checking pci_dev->is_pcie. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCIe ASPM: use pci_pcie_cap()Kenji Kaneshige2009-11-241-10/+10
| | | | | | | | | Use pci_pcie_cap() instead of pci_find_capability() to get PCIe capability offset in PCIe ASPM driver. This avoids unnecessary search in PCI configuration space. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCIe port bus: use pci_pcie_cap()Kenji Kaneshige2009-11-241-7/+7
| | | | | | | | | Use pci_pcie_cap() instead of pci_find_capability() to get PCIe capability offset in PCI Express Port Bus driver. This avoids unnecessary serarch in PCI configuration space. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCIe AER: use pci_pcie_cap()Kenji Kaneshige2009-11-242-5/+5
| | | | | | | | | Use pcie_cap() instead of pci_find_capability() to get PCIe capability offset in PCIe AER driver. This avoids unnecessary search in PCI configuration space. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: fix memory leak in aer_injectAndrew Patterson2009-11-041-1/+1
| | | | | | | | | Fixed probable typo in aer_inject cleanup code resulting in a memory leak. Acked-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: use better error return values in aer_injectAndrew Patterson2009-11-041-4/+4
| | | | | | | | | Replaced some error return values in aer_inject. Use -ENODEV when we can't find a device and -ENOTTY when the device does not support PCIe AER. Acked-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: add support for PCI domains to aer_injectAndrew Patterson2009-11-041-12/+34
| | | | | | | | Add support for PCI domains (segments) to aer_inject. Acked-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: PCIe AER: honor ACPI HEST FIRMWARE FIRST modeMatt Domsch2009-11-041-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Feedback from Hidetoshi Seto and Kenji Kaneshige incorporated. This correctly handles PCI-X bridges, PCIe root ports and endpoints, and prints debug messages when invalid/reserved types are found in the HEST. PCI devices not in domain/segment 0 are not represented in HEST, thus will be ignored. Today, the PCIe Advanced Error Reporting (AER) driver attaches itself to every PCIe root port for which BIOS reports it should, via ACPI _OSC. However, _OSC alone is insufficient for newer BIOSes. Part of ACPI 4.0 is the new APEI (ACPI Platform Error Interfaces) which is a way for OS and BIOS to handshake over which errors for which components each will handle. One table in ACPI 4.0 is the Hardware Error Source Table (HEST), where BIOS can define that errors for certain PCIe devices (or all devices), should be handled by BIOS ("Firmware First mode"), rather than be handled by the OS. Dell PowerEdge 11G server BIOS defines Firmware First mode in HEST, so that it may manage such errors, log them to the System Event Log, and possibly take other actions. The aer driver should honor this, and not attach itself to devices noted as such. Furthermore, Kenji Kaneshige reminded us to disallow changing the AER registers when respecting Firmware First mode. Platform firmware is expected to manage these, and if changes to them are allowed, it could break that firmware's behavior. The HEST parsing code may be replaced in the future by a more feature-rich implementation. This patch provides the minimum needed to prevent breakage until that implementation is available. Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: Matt Domsch <Matt_Domsch@dell.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* Merge branch 'for-linus' of ↵Linus Torvalds2009-10-122-3/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6 * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: PCI: Prevent AER driver from being loaded on non-root port PCIE devices PCI: get larger bridge ranges when space is available PCI: pci.c: fix kernel-doc notation PCI quirk: TI XIO200a erroneously reports support for fast b2b transfers PCI PM: Read device power state from register after updating it PCI: remove pci_assign_resource_fixed() PCI: PCIe portdrv: remove "-driver" from driver name
| * PCI: Prevent AER driver from being loaded on non-root port PCIE devicesKenji Kaneshige2009-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A bug was seen on boards using a PLX 8518 switch device which advertises AER on each of it's transparent bridges. The AER driver was loaded for each bridge and this driver tried to access the AER source ID register whenever an interrupt occured on the shared PCI INTX lines. The source ID register does not exist on non root port PCIE device's which advertise AER and trying to access this register causes a unsupported request error on the bridge. Thus, when the next interrupt occurs, another error is found and the non existent source ID register is accessed again, and so it goes on. The result is a spammed dmesg with unsupported request PCI express errors on the bridge device that the AER driver is loaded against. Reported-by: Malcolm Crossley <malcolm.crossley2@gefanuc.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Tested-by: Malcolm Crossley <malcolm.crossley2@gefanuc.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * PCI: PCIe portdrv: remove "-driver" from driver nameBjorn Helgaas2009-10-061-2/+1
| | | | | | | | | | | | | | | | No need to include "-driver" in the driver name. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> CC: Tom Long Nguyen <tom.l.nguyen@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | headers: remove sched.h from interrupt.hAlexey Dobriyan2009-10-111-0/+1
|/ | | | | | | | After m68k's task_thread_info() doesn't refer to current, it's possible to remove sched.h from interrupt.h and not break m68k! Many thanks to Heiko Carstens for allowing this. Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
* PCI: Disable AER with pci=nomsiAndi Kleen2009-09-171-0/+2
| | | | | | | | | | | When booting with pci=nomsi aer causes lost interrupts and lockdep inversions. So check if MSIs are not disabled before initializing the aer driver. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
generated by cgit v1.1 at 2024-05-24 13:50:47 +0000