From 4c4925c1f4ccd72002957c3e73b4f117f2bcf712 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 11 Jun 2008 12:40:13 -0400 Subject: [ARM] fix cache alignment code in memset.S This code is currently disabled, which explains why no one was affected. Signed-off-by: Nicolas Pitre Signed-off-by: Lennert Buytenhek --- arch/arm/lib/memmove.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/lib/memmove.S') diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S index ef7fddc..018522c 100644 --- a/arch/arm/lib/memmove.S +++ b/arch/arm/lib/memmove.S @@ -60,6 +60,7 @@ ENTRY(memmove) CALGN( bcs 2f ) CALGN( adr r4, 6f ) CALGN( subs r2, r2, ip ) @ C is set here + CALGN( rsb ip, ip, #32 ) CALGN( add pc, r4, ip ) PLD( pld [r1, #-4] ) @@ -139,7 +140,6 @@ ENTRY(memmove) blt 14f CALGN( ands ip, r1, #31 ) - CALGN( rsb ip, ip, #32 ) CALGN( sbcnes r4, ip, r2 ) @ C is always set here CALGN( subcc r2, r2, ip ) CALGN( bcc 15f ) -- cgit v1.1 From 2239aff6ab2b95af1f628eee7a809f21c41605b3 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Mon, 31 Mar 2008 12:38:31 -0400 Subject: [ARM] cache align destination pointer when copying memory for some processors The implementation for memory copy functions on ARM had a (disabled) provision for aligning the source pointer before loading registers with data. Turns out that aligning the _destination_ pointer is much more useful, as the read side is already sufficiently helped with the use of preload. So this changes the definition of the CALGN() macro to target the destination pointer instead, and turns it on for Feroceon processors where the gain is very noticeable. Signed-off-by: Nicolas Pitre Signed-off-by: Lennert Buytenhek --- arch/arm/lib/memmove.S | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'arch/arm/lib/memmove.S') diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S index 018522c..2e301b7 100644 --- a/arch/arm/lib/memmove.S +++ b/arch/arm/lib/memmove.S @@ -13,14 +13,6 @@ #include #include -/* - * This can be used to enable code to cacheline align the source pointer. - * Experiments on tested architectures (StrongARM and XScale) didn't show - * this a worthwhile thing to do. That might be different in the future. - */ -//#define CALGN(code...) code -#define CALGN(code...) - .text /* @@ -55,7 +47,7 @@ ENTRY(memmove) stmfd sp!, {r5 - r8} blt 5f - CALGN( ands ip, r1, #31 ) + CALGN( ands ip, r0, #31 ) CALGN( sbcnes r4, ip, r2 ) @ C is always set here CALGN( bcs 2f ) CALGN( adr r4, 6f ) @@ -139,7 +131,7 @@ ENTRY(memmove) subs r2, r2, #28 blt 14f - CALGN( ands ip, r1, #31 ) + CALGN( ands ip, r0, #31 ) CALGN( sbcnes r4, ip, r2 ) @ C is always set here CALGN( subcc r2, r2, ip ) CALGN( bcc 15f ) -- cgit v1.1