From 53d7168026a440c4cba25468a3d926ddd7ab030a Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Sat, 5 Apr 2008 21:14:03 +0100 Subject: [ARM] 4933/1: AT91CAP9 UDPHS driver: generic AT91 parts. This is patch 1 of 2 adding support for the USB High Speed Device Port on the AT91CAP9 system on chip. The AT91CAP9 uses the same UDPHS IP as the AVR32 and the AT91SAM9RL. This patch makes the generic AT91 adaptations, mainly dealing with the addition of the UDPHS UTMI clock. Signed-off-by: Stelian Pop Acked-by: Haavard Skinnemoen Acked-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91/clock.c | 42 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-at91/clock.c') diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index a33dfe4..b87772c 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -112,12 +112,34 @@ static void pmc_sys_mode(struct clk *clk, int is_on) at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); } +static void pmc_uckr_mode(struct clk *clk, int is_on) +{ + unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR); + + if (is_on) { + is_on = AT91_PMC_LOCKU; + at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); + } else + at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask)); + + do { + cpu_relax(); + } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); +} + /* USB function clocks (PLLB must be 48 MHz) */ static struct clk udpck = { .name = "udpck", .parent = &pllb, .mode = pmc_sys_mode, }; +static struct clk utmi_clk = { + .name = "utmi_clk", + .parent = &main_clk, + .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */ + .mode = pmc_uckr_mode, + .type = CLK_TYPE_PLL, +}; static struct clk uhpck = { .name = "uhpck", .parent = &pllb, @@ -361,7 +383,7 @@ static void __init init_programmable_clock(struct clk *clk) static int at91_clk_show(struct seq_file *s, void *unused) { - u32 scsr, pcsr, sr; + u32 scsr, pcsr, uckr = 0, sr; struct clk *clk; seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR)); @@ -370,6 +392,8 @@ static int at91_clk_show(struct seq_file *s, void *unused) seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); + if (cpu_is_at91cap9()) + seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR)); seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); @@ -382,6 +406,8 @@ static int at91_clk_show(struct seq_file *s, void *unused) state = (scsr & clk->pmc_mask) ? "on" : "off"; else if (clk->mode == pmc_periph_mode) state = (pcsr & clk->pmc_mask) ? "on" : "off"; + else if (clk->mode == pmc_uckr_mode) + state = (uckr & clk->pmc_mask) ? "on" : "off"; else if (clk->pmc_mask) state = (sr & clk->pmc_mask) ? "on" : "off"; else if (clk == &clk32k || clk == &main_clk) @@ -582,6 +608,17 @@ int __init at91_clock_init(unsigned long main_clock) uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); /* + * USB HS clock init + */ + if (cpu_is_at91cap9()) { + /* + * multiplier is hard-wired to 40 + * (obtain the USB High Speed 480 MHz when input is 12 MHz) + */ + utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; + } + + /* * MCK and CPU derive from one of those primary clocks. * For now, assume this parentage won't change. */ @@ -598,6 +635,9 @@ int __init at91_clock_init(unsigned long main_clock) for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) list_add_tail(&standard_pmc_clocks[i]->node, &clocks); + if (cpu_is_at91cap9()) + list_add_tail(&utmi_clk.node, &clocks); + /* MCK and CPU clock are "always on" */ clk_enable(&mck); -- cgit v1.1 From ba45ca435060614e595a107ac323a36b52619d7d Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Tue, 8 Apr 2008 13:59:18 +0100 Subject: [ARM] 4940/1: AT91: UDPHS driver: SAM9RL board and cpu integration. Adds support for the USB High Speed Device Port on the AT91SAM9RL system on chip. The AT91SAM9RL uses the same UDPHS IP as the AVR32 and the AT91CAP9 (atmel_usba_udc driver). Signed-off-by: Nicolas Ferre Acked-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91/clock.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-at91/clock.c') diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index b87772c..e8ce8f0 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -391,8 +391,9 @@ static int at91_clk_show(struct seq_file *s, void *unused) seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); - seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); - if (cpu_is_at91cap9()) + if (!cpu_is_at91sam9rl()) + seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); + if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR)); seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); @@ -610,7 +611,7 @@ int __init at91_clock_init(unsigned long main_clock) /* * USB HS clock init */ - if (cpu_is_at91cap9()) { + if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) { /* * multiplier is hard-wired to 40 * (obtain the USB High Speed 480 MHz when input is 12 MHz) @@ -635,7 +636,7 @@ int __init at91_clock_init(unsigned long main_clock) for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) list_add_tail(&standard_pmc_clocks[i]->node, &clocks); - if (cpu_is_at91cap9()) + if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) list_add_tail(&utmi_clk.node, &clocks); /* MCK and CPU clock are "always on" */ -- cgit v1.1 From 613526677a74c2b3d1b1696ea7334b2cf35155b3 Mon Sep 17 00:00:00 2001 From: sedji gaouaou Date: Thu, 10 Jul 2008 10:15:35 +0100 Subject: [ARM] 5130/4: Support for the at91sam9g20 Support for the at91sam9g20 : Atmel 400Mhz ARM 926ej-s SOC. AT91sam9g20 is an evolution of the at91sam9260 with a faster clock speed. We created a new board for this device but based the chip support directly on 9260 files with little updates. Here is the chip page on Atmel wabsite: http://atmel.com/dyn/products/product_card.asp?part_id=4337 Signed-off-by: Sedji Gaouaou Signed-off-by: Justin Waters Acked-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91/clock.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-at91/clock.c') diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index e8ce8f0..464bdbb 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -515,14 +515,19 @@ static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq) /* * PLL input between 1MHz and 32MHz per spec, but lower * frequences seem necessary in some cases so allow 100K. + * Warning: some newer products need 2MHz min. */ input = main_freq / i; + if (cpu_is_at91sam9g20() && input < 2000000) + continue; if (input < 100000) continue; if (input > 32000000) continue; mul1 = out_freq / input; + if (cpu_is_at91sam9g20() && mul > 63) + continue; if (mul1 > 2048) continue; if (mul1 < 2) @@ -582,7 +587,8 @@ int __init at91_clock_init(unsigned long main_clock) /* report if PLLA is more than mildly overclocked */ plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); - if (plla.rate_hz > 209000000) + if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000) + || (cpu_is_at91sam9g20() && plla.rate_hz > 800000000)) pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); /* @@ -597,7 +603,7 @@ int __init at91_clock_init(unsigned long main_clock) uhpck.pmc_mask = AT91RM9200_PMC_UHP; udpck.pmc_mask = AT91RM9200_PMC_UDP; at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); - } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) { + } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { uhpck.pmc_mask = AT91SAM926x_PMC_UHP; udpck.pmc_mask = AT91SAM926x_PMC_UDP; } else if (cpu_is_at91cap9()) { @@ -629,8 +635,13 @@ int __init at91_clock_init(unsigned long main_clock) freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ if (cpu_is_at91rm9200()) mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ - else - mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + else if (cpu_is_at91sam9g20()) { + mck.rate_hz = (mckr & AT91_PMC_MDIV) ? + freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ + if (mckr & AT91_PMC_PDIV) + freq /= 2; /* processor clock division */ + } else + mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ /* Register the PMC's standard clocks */ for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) -- cgit v1.1