From 07f841b7c587a3cbf481509be09ba5eda05f8d31 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 1 Oct 2008 17:11:06 +0100 Subject: [ARM] mm: enable sparsemem on clps7500 and RiscPC Signed-off-by: Russell King --- arch/arm/mach-clps7500/include/mach/memory.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/mach-clps7500/include/mach/memory.h') diff --git a/arch/arm/mach-clps7500/include/mach/memory.h b/arch/arm/mach-clps7500/include/mach/memory.h index 3326aa9..87b32db 100644 --- a/arch/arm/mach-clps7500/include/mach/memory.h +++ b/arch/arm/mach-clps7500/include/mach/memory.h @@ -32,4 +32,12 @@ #define FLUSH_BASE_PHYS 0x00000000 #define FLUSH_BASE 0xdf000000 +/* + * Sparsemem support. Each section is a maximum of 64MB. The sections + * are offset by 128MB and can cover 128MB, so that gives us a maximum + * of 29 physmem bits. + */ +#define MAX_PHYSMEM_BITS 29 +#define SECTION_SIZE_BITS 26 + #endif -- cgit v1.1