From c4236d2e7913d18d058a018f0d19473eb6a11a3c Mon Sep 17 00:00:00 2001 From: Peter 'p2' De Schrijver Date: Mon, 20 Dec 2010 14:05:07 -0600 Subject: OMAP3630: PM: Disable L2 cache while invalidating L2 cache While coming out of MPU OSWR/OFF states, L2 controller is reseted. The reset behavior is implementation specific as per ARMv7 TRM and hence $L2 needs to be invalidated before it's use. Since the AUXCTRL register is also reconfigured, disable L2 cache before invalidating it and re-enables it afterwards. This is as per Cortex-A8 ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from "public side" while, on OMAP3430, this is done in the "secure side". Cc: Kevin Hilman Cc: Tony Lindgren Acked-by: Jean Pihet Acked-by: Santosh Shilimkar [nm@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630] Signed-off-by: Nishanth Menon Signed-off-by: Eduardo Valentin Signed-off-by: Peter 'p2' De Schrijver Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm34xx.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2/pm34xx.c') diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 7dbc000..96e309d 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -996,8 +996,11 @@ void omap_push_sram_idle(void) static void __init pm_errata_configure(void) { - if (cpu_is_omap3630()) + if (cpu_is_omap3630()) { pm34xx_errata |= PM_RTA_ERRATUM_i608; + /* Enable the l2 cache toggling in sleep logic */ + enable_omap3630_toggle_l2_on_restore(); + } } static int __init omap3_pm_init(void) -- cgit v1.1