From 8f65873e47784a390949f0d61e5692dbf2a8253e Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Tue, 18 Nov 2008 17:48:22 +0800 Subject: Blackfin arch: SMP supporting patchset: Blackfin kernel and memory management code Blackfin dual core BF561 processor can support SMP like features. https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like In this patch, we provide SMP extend to Blackfin kernel and memory management code Singed-off-by: Graf Yang Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 163 +++++++++++++++++++++++++++++-------------- 1 file changed, 111 insertions(+), 52 deletions(-) (limited to 'arch/blackfin/kernel/setup.c') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 71a9a8c..c644d23 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -26,11 +26,10 @@ #include #include #include +#include #include #include -static DEFINE_PER_CPU(struct cpu, cpu_devices); - u16 _bfin_swrst; EXPORT_SYMBOL(_bfin_swrst); @@ -79,29 +78,76 @@ static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata; static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata; static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata; -void __init bfin_cache_init(void) -{ +DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data); + #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) - generate_cplb_tables(); +void __init generate_cplb_tables(void) +{ + unsigned int cpu; + + /* Generate per-CPU I&D CPLB tables */ + for (cpu = 0; cpu < num_possible_cpus(); ++cpu) + generate_cplb_tables_cpu(cpu); +} #endif +void __cpuinit bfin_setup_caches(unsigned int cpu) +{ #ifdef CONFIG_BFIN_ICACHE - bfin_icache_init(); - printk(KERN_INFO "Instruction Cache Enabled\n"); +#ifdef CONFIG_MPU + bfin_icache_init(icplb_tbl[cpu]); +#else + bfin_icache_init(icplb_tables[cpu]); +#endif #endif #ifdef CONFIG_BFIN_DCACHE - bfin_dcache_init(); - printk(KERN_INFO "Data Cache Enabled" +#ifdef CONFIG_MPU + bfin_dcache_init(dcplb_tbl[cpu]); +#else + bfin_dcache_init(dcplb_tables[cpu]); +#endif +#endif + + /* + * In cache coherence emulation mode, we need to have the + * D-cache enabled before running any atomic operation which + * might invove cache invalidation (i.e. spinlock, rwlock). + * So printk's are deferred until then. + */ +#ifdef CONFIG_BFIN_ICACHE + printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); +#endif +#ifdef CONFIG_BFIN_DCACHE + printk(KERN_INFO "Data Cache Enabled for CPU%u" # if defined CONFIG_BFIN_WB " (write-back)" # elif defined CONFIG_BFIN_WT " (write-through)" # endif - "\n"); + "\n", cpu); #endif } +void __cpuinit bfin_setup_cpudata(unsigned int cpu) +{ + struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu); + + cpudata->idle = current; + cpudata->loops_per_jiffy = loops_per_jiffy; + cpudata->cclk = get_cclk(); + cpudata->imemctl = bfin_read_IMEM_CONTROL(); + cpudata->dmemctl = bfin_read_DMEM_CONTROL(); +} + +void __init bfin_cache_init(void) +{ +#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) + generate_cplb_tables(); +#endif + bfin_setup_caches(0); +} + void __init bfin_relocate_l1_mem(void) { unsigned long l1_code_length; @@ -230,7 +276,7 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) /* record all known change-points (starting and ending addresses), omitting those that are for empty memory regions */ chgidx = 0; - for (i = 0; i < old_nr; i++) { + for (i = 0; i < old_nr; i++) { if (map[i].size != 0) { change_point[chgidx]->addr = map[i].addr; change_point[chgidx++]->pentry = &map[i]; @@ -238,13 +284,13 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) change_point[chgidx++]->pentry = &map[i]; } } - chg_nr = chgidx; /* true number of change-points */ + chg_nr = chgidx; /* true number of change-points */ /* sort change-point list by memory addresses (low -> high) */ still_changing = 1; - while (still_changing) { + while (still_changing) { still_changing = 0; - for (i = 1; i < chg_nr; i++) { + for (i = 1; i < chg_nr; i++) { /* if > , swap */ /* or, if current= & last=, swap */ if ((change_point[i]->addr < change_point[i-1]->addr) || @@ -261,10 +307,10 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) } /* create a new memmap, removing overlaps */ - overlap_entries = 0; /* number of entries in the overlap table */ - new_entry = 0; /* index for creating new memmap entries */ - last_type = 0; /* start with undefined memory type */ - last_addr = 0; /* start with 0 as last starting address */ + overlap_entries = 0; /* number of entries in the overlap table */ + new_entry = 0; /* index for creating new memmap entries */ + last_type = 0; /* start with undefined memory type */ + last_addr = 0; /* start with 0 as last starting address */ /* loop through change-points, determining affect on the new memmap */ for (chgidx = 0; chgidx < chg_nr; chgidx++) { /* keep track of all overlapping memmap entries */ @@ -286,14 +332,14 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) if (overlap_list[i]->type > current_type) current_type = overlap_list[i]->type; /* continue building up new memmap based on this information */ - if (current_type != last_type) { + if (current_type != last_type) { if (last_type != 0) { new_map[new_entry].size = change_point[chgidx]->addr - last_addr; /* move forward only if the new size was non-zero */ if (new_map[new_entry].size != 0) if (++new_entry >= BFIN_MEMMAP_MAX) - break; /* no more space left for new entries */ + break; /* no more space left for new entries */ } if (current_type != 0) { new_map[new_entry].addr = change_point[chgidx]->addr; @@ -303,9 +349,9 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) last_type = current_type; } } - new_nr = new_entry; /* retain count for new entries */ + new_nr = new_entry; /* retain count for new entries */ - /* copy new mapping into original location */ + /* copy new mapping into original location */ memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry)); *pnr_map = new_nr; @@ -361,7 +407,6 @@ static __init int parse_memmap(char *arg) * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region * @ from to +, type RAM * $ from to +, type RESERVED - * */ static __init void parse_cmdline_early(char *cmdline_p) { @@ -383,12 +428,10 @@ static __init void parse_cmdline_early(char *cmdline_p) if (*to != ' ') { if (*to == '$' || *(to + 1) == '$') - reserved_mem_dcache_on = - 1; + reserved_mem_dcache_on = 1; if (*to == '#' || *(to + 1) == '#') - reserved_mem_icache_on = - 1; + reserved_mem_icache_on = 1; } } } else if (!memcmp(to, "earlyprintk=", 12)) { @@ -417,9 +460,8 @@ static __init void parse_cmdline_early(char *cmdline_p) * [_ramend - DMA_UNCACHED_REGION, * _ramend]: uncached DMA region * [_ramend, physical_mem_end]: memory not managed by kernel - * */ -static __init void memory_setup(void) +static __init void memory_setup(void) { #ifdef CONFIG_MTD_UCLINUX unsigned long mtd_phys = 0; @@ -436,7 +478,7 @@ static __init void memory_setup(void) memory_end = _ramend - DMA_UNCACHED_REGION; #ifdef CONFIG_MPU - /* Round up to multiple of 4MB. */ + /* Round up to multiple of 4MB */ memory_start = (_ramstart + 0x3fffff) & ~0x3fffff; #else memory_start = PAGE_ALIGN(_ramstart); @@ -616,7 +658,7 @@ static __init void setup_bootmem_allocator(void) end_pfn = memory_end >> PAGE_SHIFT; /* - * give all the memory to the bootmap allocator, tell it to put the + * give all the memory to the bootmap allocator, tell it to put the * boot mem_map at the start of memory. */ bootmap_size = init_bootmem_node(NODE_DATA(0), @@ -791,7 +833,11 @@ void __init setup_arch(char **cmdline_p) bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT); #endif +#ifdef CONFIG_SMP + if (_bfin_swrst & SWRST_DBL_FAULT_A) { +#else if (_bfin_swrst & RESET_DOUBLE) { +#endif printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n"); #ifdef CONFIG_DEBUG_DOUBLEFAULT /* We assume the crashing kernel, and the current symbol table match */ @@ -835,7 +881,7 @@ void __init setup_arch(char **cmdline_p) printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", - cclk / 1000000, sclk / 1000000); + cclk / 1000000, sclk / 1000000); if (ANOMALY_05000273 && (cclk >> 1) <= sclk) printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n"); @@ -867,18 +913,21 @@ void __init setup_arch(char **cmdline_p) BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start != SAFE_USER_INSTRUCTION - FIXED_CODE_START); +#ifdef CONFIG_SMP + platform_init_cpus(); +#endif init_exception_vectors(); - bfin_cache_init(); + bfin_cache_init(); /* Initialize caches for the boot CPU */ } static int __init topology_init(void) { - int cpu; + unsigned int cpu; + /* Record CPU-private information for the boot processor. */ + bfin_setup_cpudata(0); for_each_possible_cpu(cpu) { - struct cpu *c = &per_cpu(cpu_devices, cpu); - - register_cpu(c, cpu); + register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu); } return 0; @@ -983,15 +1032,15 @@ static int show_cpuinfo(struct seq_file *m, void *v) char *cpu, *mmu, *fpu, *vendor, *cache; uint32_t revid; - u_long cclk = 0, sclk = 0; + u_long sclk = 0; u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0; + struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, *(unsigned int *)v); cpu = CPU; mmu = "none"; fpu = "none"; revid = bfin_revid(); - cclk = get_cclk(); sclk = get_sclk(); switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) { @@ -1003,10 +1052,8 @@ static int show_cpuinfo(struct seq_file *m, void *v) break; } - seq_printf(m, "processor\t: %d\n" - "vendor_id\t: %s\n", - *(unsigned int *)v, - vendor); + seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", + *(unsigned int *)v, vendor); if (CPUID == bfin_cpuid()) seq_printf(m, "cpu family\t: 0x%04x\n", CPUID); @@ -1016,7 +1063,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n" "stepping\t: %d\n", - cpu, cclk/1000000, sclk/1000000, + cpu, cpudata->cclk/1000000, sclk/1000000, #ifdef CONFIG_MPU "mpu on", #else @@ -1025,16 +1072,16 @@ static int show_cpuinfo(struct seq_file *m, void *v) revid); seq_printf(m, "cpu MHz\t\t: %lu.%03lu/%lu.%03lu\n", - cclk/1000000, cclk%1000000, + cpudata->cclk/1000000, cpudata->cclk%1000000, sclk/1000000, sclk%1000000); seq_printf(m, "bogomips\t: %lu.%02lu\n" "Calibration\t: %lu loops\n", - (loops_per_jiffy * HZ) / 500000, - ((loops_per_jiffy * HZ) / 5000) % 100, - (loops_per_jiffy * HZ)); + (cpudata->loops_per_jiffy * HZ) / 500000, + ((cpudata->loops_per_jiffy * HZ) / 5000) % 100, + (cpudata->loops_per_jiffy * HZ)); /* Check Cache configutation */ - switch (bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) { + switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) { case ACACHE_BSRAM: cache = "dbank-A/B\t: cache/sram"; dcache_size = 16; @@ -1058,10 +1105,10 @@ static int show_cpuinfo(struct seq_file *m, void *v) } /* Is it turned on? */ - if ((bfin_read_DMEM_CONTROL() & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE)) + if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE)) dcache_size = 0; - if ((bfin_read_IMEM_CONTROL() & (IMC | ENICPLB)) != (IMC | ENICPLB)) + if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB)) icache_size = 0; seq_printf(m, "cache size\t: %d KB(L1 icache) " @@ -1086,8 +1133,13 @@ static int show_cpuinfo(struct seq_file *m, void *v) "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n", dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS, BFIN_DLINES); +#ifdef __ARCH_SYNC_CORE_DCACHE + seq_printf(m, + "SMP Dcache Flushes\t: %lu\n\n", + per_cpu(cpu_data, *(unsigned int *)v).dcache_invld_count); +#endif #ifdef CONFIG_BFIN_ICACHE_LOCK - switch ((bfin_read_IMEM_CONTROL() >> 3) & WAYALL_L) { + switch ((cpudata->imemctl >> 3) & WAYALL_L) { case WAY0_L: seq_printf(m, "Way0 Locked-Down\n"); break; @@ -1137,6 +1189,12 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "No Ways are locked\n"); } #endif + if (*(unsigned int *)v != NR_CPUS-1) + return 0; + +#if L2_LENGTH + seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); +#endif seq_printf(m, "board name\t: %s\n", bfin_board_name); seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); @@ -1144,6 +1202,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) ((int)memory_end - (int)_stext) >> 10, _stext, (void *)memory_end); + seq_printf(m, "\n"); return 0; } -- cgit v1.1 From a5f0717e51c5fe6cdaf885b7f621ba48ae745bfb Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 18 Nov 2008 18:04:31 +0800 Subject: Blackfin arch: Fix bug - change cpufreq doesn't take effect on bf537 now CCLK is variable: get current CCLK in show_cpuinfo Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/blackfin/kernel/setup.c') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index c644d23..0a54367 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -1032,7 +1032,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) char *cpu, *mmu, *fpu, *vendor, *cache; uint32_t revid; - u_long sclk = 0; + u_long sclk, cclk; u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0; struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, *(unsigned int *)v); @@ -1042,6 +1042,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) revid = bfin_revid(); sclk = get_sclk(); + cclk = get_cclk(); switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) { case 0xca: @@ -1063,7 +1064,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n" "stepping\t: %d\n", - cpu, cpudata->cclk/1000000, sclk/1000000, + cpu, cclk/1000000, sclk/1000000, #ifdef CONFIG_MPU "mpu on", #else @@ -1072,7 +1073,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) revid); seq_printf(m, "cpu MHz\t\t: %lu.%03lu/%lu.%03lu\n", - cpudata->cclk/1000000, cpudata->cclk%1000000, + cclk/1000000, cclk%1000000, sclk/1000000, sclk%1000000); seq_printf(m, "bogomips\t: %lu.%02lu\n" "Calibration\t: %lu loops\n", -- cgit v1.1 From 1ea9925553caad6ea5068b4652596f149e0be9c3 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 7 Jan 2009 23:14:38 +0800 Subject: Blackfin arch: delete now unused "cclk" member of blackfin_cpudata Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/blackfin/kernel/setup.c') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 0a54367..b147ed9 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -135,7 +135,6 @@ void __cpuinit bfin_setup_cpudata(unsigned int cpu) cpudata->idle = current; cpudata->loops_per_jiffy = loops_per_jiffy; - cpudata->cclk = get_cclk(); cpudata->imemctl = bfin_read_IMEM_CONTROL(); cpudata->dmemctl = bfin_read_DMEM_CONTROL(); } -- cgit v1.1 From dd3dd384df7f9f77fba6875a606e5a663510cd1d Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 7 Jan 2009 23:14:39 +0800 Subject: Blackfin arch: rewrite dma_memcpy() and dma in/out functions - unify all dma in/out functions (takes ~35 lines of code now) - unify dma_memcpy with dma in/out functions (1 place that touches MDMA0 registers) - add support for 32bit transfers - cleanup dma_memcpy code to be much more readable - irqs are disabled only while programming MDMA registers rather than the entire transaction Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/blackfin/kernel/setup.c') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index b147ed9..56b8b4c 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -154,6 +154,8 @@ void __init bfin_relocate_l1_mem(void) unsigned long l1_data_b_length; unsigned long l2_length; + blackfin_dma_early_init(); + l1_code_length = _etext_l1 - _stext_l1; if (l1_code_length > L1_CODE_LENGTH) panic("L1 Instruction SRAM Overflow\n"); -- cgit v1.1 From 259fea42e66e62226c310a6646049b99912af7cc Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 7 Jan 2009 23:14:39 +0800 Subject: Blackfin arch: include linux/mm.h since we use PAGE_ALIGN and such Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/blackfin/kernel/setup.c') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 56b8b4c..fff8c7c 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include -- cgit v1.1 From 275123e8ab59ee6379dcccbd05c5fcc418801b64 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 7 Jan 2009 23:14:39 +0800 Subject: Blackfin arch: show_cpuinfo - consolidate ugly casts rather than use *(unsigned int *)v everywhere, do this once with a local cpu_num variable Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) (limited to 'arch/blackfin/kernel/setup.c') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index fff8c7c..638da7b 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -1033,10 +1033,10 @@ static int show_cpuinfo(struct seq_file *m, void *v) { char *cpu, *mmu, *fpu, *vendor, *cache; uint32_t revid; - + int cpu_num = *(unsigned int *)v; u_long sclk, cclk; u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0; - struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, *(unsigned int *)v); + struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num); cpu = CPU; mmu = "none"; @@ -1055,8 +1055,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) break; } - seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", - *(unsigned int *)v, vendor); + seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor); if (CPUID == bfin_cpuid()) seq_printf(m, "cpu family\t: 0x%04x\n", CPUID); @@ -1137,9 +1136,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS, BFIN_DLINES); #ifdef __ARCH_SYNC_CORE_DCACHE - seq_printf(m, - "SMP Dcache Flushes\t: %lu\n\n", - per_cpu(cpu_data, *(unsigned int *)v).dcache_invld_count); + seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count); #endif #ifdef CONFIG_BFIN_ICACHE_LOCK switch ((cpudata->imemctl >> 3) & WAYALL_L) { @@ -1192,12 +1189,12 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "No Ways are locked\n"); } #endif - if (*(unsigned int *)v != NR_CPUS-1) + + if (cpu_num != num_possible_cpus() - 1) return 0; -#if L2_LENGTH - seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); -#endif + if (L2_LENGTH) + seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); seq_printf(m, "board name\t: %s\n", bfin_board_name); seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); -- cgit v1.1 From 7f1e2f98bd29f51edd64e0c15b10d9a18a7af4e1 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 7 Jan 2009 23:14:38 +0800 Subject: Blackfin arch: allow clkin_hz to be specified on the command line Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) (limited to 'arch/blackfin/kernel/setup.c') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 638da7b..c05e5e3 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -81,6 +81,8 @@ static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata; DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data); +static int early_init_clkin_hz(char *buf); + #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) void __init generate_cplb_tables(void) { @@ -436,6 +438,9 @@ static __init void parse_cmdline_early(char *cmdline_p) reserved_mem_icache_on = 1; } } + } else if (!memcmp(to, "clkin_hz=", 9)) { + to += 9; + early_init_clkin_hz(to); } else if (!memcmp(to, "earlyprintk=", 12)) { to += 12; setup_early_printk(to); @@ -937,6 +942,19 @@ static int __init topology_init(void) subsys_initcall(topology_init); +/* Get the input clock frequency */ +static u_long cached_clkin_hz = CONFIG_CLKIN_HZ; +static u_long get_clkin_hz(void) +{ + return cached_clkin_hz; +} +static int __init early_init_clkin_hz(char *buf) +{ + cached_clkin_hz = simple_strtoul(buf, NULL, 0); + return 1; +} +early_param("clkin_hz=", early_init_clkin_hz); + /* Get the voltage input multiplier */ static u_long cached_vco_pll_ctl, cached_vco; static u_long get_vco(void) @@ -953,7 +971,7 @@ static u_long get_vco(void) if (0 == msel) msel = 64; - cached_vco = CONFIG_CLKIN_HZ; + cached_vco = get_clkin_hz(); cached_vco >>= (1 & pll_ctl); /* DF bit */ cached_vco *= msel; return cached_vco; @@ -966,7 +984,7 @@ u_long get_cclk(void) u_long csel, ssel; if (bfin_read_PLL_STAT() & 0x1) - return CONFIG_CLKIN_HZ; + return get_clkin_hz(); ssel = bfin_read_PLL_DIV(); if (ssel == cached_cclk_pll_div) @@ -991,7 +1009,7 @@ u_long get_sclk(void) u_long ssel; if (bfin_read_PLL_STAT() & 0x1) - return CONFIG_CLKIN_HZ; + return get_clkin_hz(); ssel = bfin_read_PLL_DIV(); if (ssel == cached_sclk_pll_div) -- cgit v1.1 From 508808cda6c39819f51b58e95ba5c6222acea222 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 7 Jan 2009 23:14:38 +0800 Subject: Blackfin arch: do not allow people to pass in a diff clkin_hz value do not allow people to pass in a diff clkin_hz value when reprogramming clocks -- it is too late currently Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/blackfin/kernel/setup.c') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index c05e5e3..4dffb91 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -951,6 +951,10 @@ static u_long get_clkin_hz(void) static int __init early_init_clkin_hz(char *buf) { cached_clkin_hz = simple_strtoul(buf, NULL, 0); +#ifdef BFIN_KERNEL_CLOCK + if (cached_clkin_hz != CONFIG_CLKIN_HZ) + panic("cannot change clkin_hz when reprogramming clocks"); +#endif return 1; } early_param("clkin_hz=", early_init_clkin_hz); -- cgit v1.1 From 7419a327f6264bef869b195497aaf03b72ca17b7 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Wed, 7 Jan 2009 23:14:39 +0800 Subject: Blackfin arch: panic when running on a chip rev below what we are compiled for If we are running on a chip revision below what we are compiled for, there will be missing anomaly workarounds, and a panic is inevitable. Do is sooner, rather than later, so people don't look for bugs that already have workarounds (that they turned off). Signed-off-by: Robin Getz Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/blackfin/kernel/setup.c') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 4dffb91..d3d37e7 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -876,9 +876,12 @@ void __init setup_arch(char **cmdline_p) if (bfin_compiled_revid() == -1) printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", bfin_revid()); - else if (bfin_compiled_revid() != 0xffff) + else if (bfin_compiled_revid() != 0xffff) { printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", bfin_compiled_revid(), bfin_revid()); + if (bfin_compiled_revid() > bfin_revid()) + panic("Error: you are missing anomaly workarounds for this rev\n"); + } } if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", -- cgit v1.1 From dbdf20db537a5369c65330f878ad4905020a8bfa Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Wed, 7 Jan 2009 23:14:38 +0800 Subject: Blackfin arch: Faster C implementation of no-MPU CPLB handler This is a mixture ofcMichael McTernan's patch and the existing cplb-mpu code. We ditch the old cplb-nompu implementation, which is a good example of why a good algorithm in a HLL is preferrable to a bad algorithm written in assembly. Rather than try to construct a table of all posible CPLBs and search it, we just create a (smaller) table of memory regions and their attributes. Some of the data structures are now unified for both the mpu and nompu cases. A lot of needless complexity in cplbinit.c is removed. Further optimizations: * compile cplbmgr.c with a lot of -ffixed-reg options, and omit saving these registers on the stack when entering a CPLB exception. * lose cli/nop/nop/sti sequences for some workarounds - these don't * make sense in an exception context Additional code unification should be possible after this. [Mike Frysinger : - convert CPP if statements to C if statements - remove redundant statements - use a do...while loop rather than a for loop to get slightly better optimization and to avoid gcc "may be used uninitialized" warnings ... we know that the [id]cplb_nr_bounds variables will never be 0, so this is OK - the no-mpu code was the last user of MAX_MEM_SIZE and with that rewritten, we can punt it - add some BUG_ON() checks to make sure we dont overflow the small cplb_bounds array - add i/d cplb entries for the bootrom because there is functions/data in there we want to access - we do not need a NULL trailing entry as any time we access the bounds arrays, we use the nr_bounds variable ] Signed-off-by: Michael McTernan Signed-off-by: Mike Frysinger Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'arch/blackfin/kernel/setup.c') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index d3d37e7..20d04a1 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -88,6 +88,7 @@ void __init generate_cplb_tables(void) { unsigned int cpu; + generate_cplb_tables_all(); /* Generate per-CPU I&D CPLB tables */ for (cpu = 0; cpu < num_possible_cpus(); ++cpu) generate_cplb_tables_cpu(cpu); @@ -97,19 +98,11 @@ void __init generate_cplb_tables(void) void __cpuinit bfin_setup_caches(unsigned int cpu) { #ifdef CONFIG_BFIN_ICACHE -#ifdef CONFIG_MPU bfin_icache_init(icplb_tbl[cpu]); -#else - bfin_icache_init(icplb_tables[cpu]); -#endif #endif #ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_MPU bfin_dcache_init(dcplb_tbl[cpu]); -#else - bfin_dcache_init(dcplb_tables[cpu]); -#endif #endif /* -- cgit v1.1 From e32f55d9dbffd2ca16e0bb4ea7156b56741b78cd Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 7 Jan 2009 23:14:39 +0800 Subject: Blackfin arch: rewrite get_sclk()/get_vco() rewrite get_sclk()/get_vco() based on the assumption sclk/vco never changes (since today it cannot) Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) (limited to 'arch/blackfin/kernel/setup.c') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 20d04a1..b2a8113 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -956,17 +956,18 @@ static int __init early_init_clkin_hz(char *buf) early_param("clkin_hz=", early_init_clkin_hz); /* Get the voltage input multiplier */ -static u_long cached_vco_pll_ctl, cached_vco; static u_long get_vco(void) { - u_long msel; + static u_long cached_vco; + u_long msel, pll_ctl; - u_long pll_ctl = bfin_read_PLL_CTL(); - if (pll_ctl == cached_vco_pll_ctl) + /* The assumption here is that VCO never changes at runtime. + * If, someday, we support that, then we'll have to change this. + */ + if (cached_vco) return cached_vco; - else - cached_vco_pll_ctl = pll_ctl; + pll_ctl = bfin_read_PLL_CTL(); msel = (pll_ctl >> 9) & 0x3F; if (0 == msel) msel = 64; @@ -978,9 +979,9 @@ static u_long get_vco(void) } /* Get the Core clock */ -static u_long cached_cclk_pll_div, cached_cclk; u_long get_cclk(void) { + static u_long cached_cclk_pll_div, cached_cclk; u_long csel, ssel; if (bfin_read_PLL_STAT() & 0x1) @@ -1003,21 +1004,21 @@ u_long get_cclk(void) EXPORT_SYMBOL(get_cclk); /* Get the System clock */ -static u_long cached_sclk_pll_div, cached_sclk; u_long get_sclk(void) { + static u_long cached_sclk; u_long ssel; + /* The assumption here is that SCLK never changes at runtime. + * If, someday, we support that, then we'll have to change this. + */ + if (cached_sclk) + return cached_sclk; + if (bfin_read_PLL_STAT() & 0x1) return get_clkin_hz(); - ssel = bfin_read_PLL_DIV(); - if (ssel == cached_sclk_pll_div) - return cached_sclk; - else - cached_sclk_pll_div = ssel; - - ssel &= 0xf; + ssel = bfin_read_PLL_DIV() & 0xf; if (0 == ssel) { printk(KERN_WARNING "Invalid System Clock\n"); ssel = 1; -- cgit v1.1