From 47740eb887796608fb4c629aa6b8507a2fb6c0eb Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sun, 19 Apr 2009 03:21:22 +0200 Subject: MIPS: Enable CLO / CLZ instructions via separate CPU property This is useful for IDT RC32332, RC32334 and NEC VR5500 processors which do not implement the full MIPS32 / MIPS64 architecture. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/bitops.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips/include/asm/bitops.h') diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index bac4a96..b1e9e97 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -567,7 +567,7 @@ static inline unsigned long __fls(unsigned long word) int num; if (BITS_PER_LONG == 32 && - __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { + __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { __asm__( " .set push \n" " .set mips32 \n" @@ -644,7 +644,7 @@ static inline int fls(int x) { int r; - if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { + if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { __asm__("clz %0, %1" : "=r" (x) : "r" (x)); return 32 - x; -- cgit v1.1