From 6f329468f3086e9d8f3832930fdb09ab3769176b Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 10 Feb 2010 15:12:48 -0800 Subject: MIPS: Give Octeon+ CPUs their own cputype. This allows us to treat them differently at runtime. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/951/ Patchwork: http://patchwork.linux-mips.org/patch/987/ Signed-off-by: Ralf Baechle --- arch/mips/mm/c-octeon.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/mips/mm') diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index af85959..0f9c488 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -183,6 +183,7 @@ static void __cpuinit probe_octeon(void) switch (c->cputype) { case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: config1 = read_c0_config1(); c->icache.linesz = 2 << ((config1 >> 19) & 7); c->icache.sets = 64 << ((config1 >> 22) & 7); @@ -192,10 +193,10 @@ static void __cpuinit probe_octeon(void) c->icache.sets * c->icache.ways * c->icache.linesz; c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; c->dcache.linesz = 128; - if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) - c->dcache.sets = 1; /* CN3XXX has one Dcache set */ - else + if (c->cputype == CPU_CAVIUM_OCTEON_PLUS) c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ + else + c->dcache.sets = 1; /* CN3XXX has one Dcache set */ c->dcache.ways = 64; dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; -- cgit v1.1