From f658bcfb2607bf0808966a69cf74135ce98e5c2d Mon Sep 17 00:00:00 2001 From: Hans Rosenfeld Date: Fri, 29 Oct 2010 17:14:32 +0200 Subject: x86, cacheinfo: Cleanup L3 cache index disable support Adaptions to the changes of the AMD northbridge caching code: instead of a bool in each l3 struct, use a flag in amd_northbridges.flags to indicate L3 cache index disable support; use a pointer to the whole northbridge instead of the misc device in the l3 struct; simplify the initialisation; dynamically generate sysfs attribute array. Signed-off-by: Hans Rosenfeld Signed-off-by: Borislav Petkov --- arch/x86/include/asm/amd_nb.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/x86/include/asm/amd_nb.h') diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 4d7ec7d..6aee50d 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -25,6 +25,7 @@ struct amd_northbridge_info { extern struct amd_northbridge_info amd_northbridges; #define AMD_NB_GART 0x1 +#define AMD_NB_L3_INDEX_DISABLE 0x2 #ifdef CONFIG_AMD_NB -- cgit v1.1