From a2757b6fab6dee3dbf43bdb7d7226d03747fbdb1 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Fri, 9 Jul 2010 10:45:17 -0700 Subject: agp/intel: Add actual definitions of the Sandybridge PTE caching bits. --- drivers/char/agp/intel-agp.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/char/agp/intel-agp.h') diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h index 2547465..c05e3e5 100644 --- a/drivers/char/agp/intel-agp.h +++ b/drivers/char/agp/intel-agp.h @@ -60,6 +60,12 @@ #define I810_PTE_LOCAL 0x00000002 #define I810_PTE_VALID 0x00000001 #define I830_PTE_SYSTEM_CACHED 0x00000006 +/* GT PTE cache control fields */ +#define GEN6_PTE_UNCACHED 0x00000002 +#define GEN6_PTE_LLC 0x00000004 +#define GEN6_PTE_LLC_MLC 0x00000006 +#define GEN6_PTE_GFDT 0x00000008 + #define I810_SMRAM_MISCC 0x70 #define I810_GFX_MEM_WIN_SIZE 0x00010000 #define I810_GFX_MEM_WIN_32M 0x00010000 -- cgit v1.1