From 155285c4775b7027b01a5b744c721ae43cced798 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 16 May 2006 20:16:41 +0400 Subject: NAND: AMD Au1550 driver reads write-only register During the last cleanup of the AMD Au1550 NAND driver the old buglet was reintroduced: as the MEM_STNDCTL register is write-only and seem to always read as 0x31, read-modify-write to it done in au1xxx_nand_init() will have the side effect of enabling -RCS0/1 pin override (via bits 4/5 of this reg.), thus possibly causing a contention on the static bus when the NOR flash (using -RCS0) or board control status registers (using -RCS2) are read. Luckily, this goes away with a first NAND access, since au1550_hwcontrol() doesn't try to read this register before writing anymore. Signed-off-by: Sergei Shtylyov Signed-off-by: David Woodhouse --- drivers/mtd/nand/au1550nd.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/mtd/nand/au1550nd.c') diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 861fb96..839b35a 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -347,11 +347,9 @@ static int __init au1xxx_nand_init(void) au1550_mtd->priv = this; au1550_mtd->owner = THIS_MODULE; - /* disable interrupts */ - au_writel(au_readl(MEM_STNDCTL) & ~(1 << 8), MEM_STNDCTL); - /* disable NAND boot */ - au_writel(au_readl(MEM_STNDCTL) & ~(1 << 0), MEM_STNDCTL); + /* MEM_STNDCTL: disable ints, disable nand boot */ + au_writel(0, MEM_STNDCTL); #ifdef CONFIG_MIPS_PB1550 /* set gpio206 high */ -- cgit v1.1