From 8b99e68c0a40bcf082c1ba9aaad83cca4def8cec Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 13 Oct 2010 09:59:17 +0100 Subject: drm/i915: restore fixed FDI link rate on Sandybridge FDI_PLL_BIOS_0 register is for Ironlake only, don't apply to Sandybridge. Original-patch-by: Zhenyu Wang Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index faacbbd..cda36b3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -345,8 +345,11 @@ intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, static inline u32 /* units of 100MHz */ intel_fdi_link_freq(struct drm_device *dev) { - struct drm_i915_private *dev_priv = dev->dev_private; - return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; + if (IS_GEN5(dev)) { + struct drm_i915_private *dev_priv = dev->dev_private; + return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; + } else + return 27; } static const intel_limit_t intel_limits_i8xx_dvo = { -- cgit v1.1