aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/boot/dts/p1020rdb.dts
blob: 22f64b62d7f64039020013ab317da0429416f9f9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
/*
 * P1020 RDB Device Tree Source
 *
 * Copyright 2009 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;
/ {
	model = "fsl,P1020";
	compatible = "fsl,P1020RDB";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		pci0 = &pci0;
		pci1 = &pci1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,P1020@0 {
			device_type = "cpu";
			reg = <0x0>;
			next-level-cache = <&L2>;
		};

		PowerPC,P1020@1 {
			device_type = "cpu";
			reg = <0x1>;
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
	};

	localbus@ffe05000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
		reg = <0 0xffe05000 0 0x1000>;
		interrupts = <19 2>;
		interrupt-parent = <&mpic>;

		/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
		ranges = <0x0 0x0 0x0 0xef000000 0x01000000
			  0x1 0x0 0x0 0xffa00000 0x00040000
			  0x2 0x0 0x0 0xffb00000 0x00020000>;

		nor@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x1000000>;
			bank-width = <2>;
			device-width = <1>;

			partition@0 {
				/* This location must not be altered  */
				/* 256KB for Vitesse 7385 Switch firmware */
				reg = <0x0 0x00040000>;
				label = "NOR (RO) Vitesse-7385 Firmware";
				read-only;
			};

			partition@40000 {
				/* 256KB for DTB Image */
				reg = <0x00040000 0x00040000>;
				label = "NOR (RO) DTB Image";
				read-only;
			};

			partition@80000 {
				/* 3.5 MB for Linux Kernel Image */
				reg = <0x00080000 0x00380000>;
				label = "NOR (RO) Linux Kernel Image";
				read-only;
			};

			partition@400000 {
				/* 11MB for JFFS2 based Root file System */
				reg = <0x00400000 0x00b00000>;
				label = "NOR (RW) JFFS2 Root File System";
			};

			partition@f00000 {
				/* This location must not be altered  */
				/* 512KB for u-boot Bootloader Image */
				/* 512KB for u-boot Environment Variables */
				reg = <0x00f00000 0x00100000>;
				label = "NOR (RO) U-Boot Image";
				read-only;
			};
		};

		nand@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,p1020-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <0x1 0x0 0x40000>;

			partition@0 {
				/* This location must not be altered  */
				/* 1MB for u-boot Bootloader Image */
				reg = <0x0 0x00100000>;
				label = "NAND (RO) U-Boot Image";
				read-only;
			};

			partition@100000 {
				/* 1MB for DTB Image */
				reg = <0x00100000 0x00100000>;
				label = "NAND (RO) DTB Image";
				read-only;
			};

			partition@200000 {
				/* 4MB for Linux Kernel Image */
				reg = <0x00200000 0x00400000>;
				label = "NAND (RO) Linux Kernel Image";
				read-only;
			};

			partition@600000 {
				/* 4MB for Compressed Root file System Image */
				reg = <0x00600000 0x00400000>;
				label = "NAND (RO) Compressed RFS Image";
				read-only;
			};

			partition@a00000 {
				/* 7MB for JFFS2 based Root file System */
				reg = <0x00a00000 0x00700000>;
				label = "NAND (RW) JFFS2 Root File System";
			};

			partition@1100000 {
				/* 15MB for JFFS2 based Root file System */
				reg = <0x01100000 0x00f00000>;
				label = "NAND (RW) Writable User area";
			};
		};

		L2switch@2,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "vitesse-7385";
			reg = <0x2 0x0 0x20000>;
		};

	};

	soc@ffe00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "fsl,p1020-immr", "simple-bus";
		ranges = <0x0  0x0 0xffe00000 0x100000>;
		bus-frequency = <0>;		// Filled out by uboot.

		ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <12>;
		};

		ecm@1000 {
			compatible = "fsl,p1020-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <16 2>;
			interrupt-parent = <&mpic>;
		};

		memory-controller@2000 {
			compatible = "fsl,p1020-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
			rtc@68 {
				compatible = "dallas,ds1339";
				reg = <0x68>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		spi@7000 {
			cell-index = <0>;
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,espi";
			reg = <0x7000 0x1000>;
			interrupts = <59 0x2>;
			interrupt-parent = <&mpic>;
			mode = "cpu";

			fsl_m25p80@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "fsl,espi-flash";
				reg = <0>;
				linux,modalias = "fsl_m25p80";
				modal = "s25sl128b";
				spi-max-frequency = <50000000>;
				mode = <0>;

				partition@0 {
					/* 512KB for u-boot Bootloader Image */
					reg = <0x0 0x00080000>;
					label = "SPI (RO) U-Boot Image";
					read-only;
				};

				partition@80000 {
					/* 512KB for DTB Image */
					reg = <0x00080000 0x00080000>;
					label = "SPI (RO) DTB Image";
					read-only;
				};

				partition@100000 {
					/* 4MB for Linux Kernel Image */
					reg = <0x00100000 0x00400000>;
					label = "SPI (RO) Linux Kernel Image";
					read-only;
				};

				partition@500000 {
					/* 4MB for Compressed RFS Image */
					reg = <0x00500000 0x00400000>;
					label = "SPI (RO) Compressed RFS Image";
					read-only;
				};

				partition@900000 {
					/* 7MB for JFFS2 based RFS */
					reg = <0x00900000 0x00700000>;
					label = "SPI (RW) JFFS2 RFS";
				};
			};
		};

		gpio: gpio-controller@f000 {
			#gpio-cells = <2>;
			compatible = "fsl,mpc8572-gpio";
			reg = <0xf000 0x100>;
			interrupts = <47 0x2>;
			interrupt-parent = <&mpic>;
			gpio-controller;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,p1020-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x40000>; // L2,256K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		mdio@24000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,etsec2-mdio";
			reg = <0x24000 0x1000 0xb0030 0x4>;

			phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <3 1>;
				reg = <0x0>;
			};

			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
				interrupts = <2 1>;
				reg = <0x1>;
			};
		};

		mdio@25000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,etsec2-tbi";
			reg = <0x25000 0x1000 0xb1030 0x4>;

			tbi0: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		enet0: ethernet@b0000 {
			#address-cells = <1>;
			#size-cells = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "fsl,etsec2";
			fsl,num_rx_queues = <0x8>;
			fsl,num_tx_queues = <0x8>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupt-parent = <&mpic>;
			fixed-link = <1 1 1000 0 0>;
			phy-connection-type = "rgmii-id";

			queue-group@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xb0000 0x1000>;
				interrupts = <29 2 30 2 34 2>;
			};

			queue-group@1 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xb4000 0x1000>;
				interrupts = <17 2 18 2 24 2>;
			};
		};

		enet1: ethernet@b1000 {
			#address-cells = <1>;
			#size-cells = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "fsl,etsec2";
			fsl,num_rx_queues = <0x8>;
			fsl,num_tx_queues = <0x8>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
			tbi-handle = <&tbi0>;
			phy-connection-type = "sgmii";

			queue-group@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xb1000 0x1000>;
				interrupts = <35 2 36 2 40 2>;
			};

			queue-group@1 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xb5000 0x1000>;
				interrupts = <51 2 52 2 67 2>;
			};
		};

		enet2: ethernet@b2000 {
			#address-cells = <1>;
			#size-cells = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "fsl,etsec2";
			fsl,num_rx_queues = <0x8>;
			fsl,num_tx_queues = <0x8>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";

			queue-group@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xb2000 0x1000>;
				interrupts = <31 2 32 2 33 2>;
			};

			queue-group@1 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xb6000 0x1000>;
				interrupts = <25 2 26 2 27 2>;
			};
		};

		usb@22000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl-usb2-dr";
			reg = <0x22000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <28 0x2>;
			phy_type = "ulpi";
		};

		/* USB2 is shared with localbus, so it must be disabled
		   by default. We can't put 'status = "disabled";' here
		   since U-Boot doesn't clear the status property when
		   it enables USB2. OTOH, U-Boot does create a new node
		   when there isn't any. So, just comment it out.
		usb@23000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl-usb2-dr";
			reg = <0x23000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <46 0x2>;
			phy_type = "ulpi";
		};
		*/

		sdhci@2e000 {
			compatible = "fsl,p1020-esdhc", "fsl,esdhc";
			reg = <0x2e000 0x1000>;
			interrupts = <72 0x2>;
			interrupt-parent = <&mpic>;
			/* Filled in by U-Boot */
			clock-frequency = <0>;
		};

		crypto@30000 {
			compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
				     "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2 58 2>;
			interrupt-parent = <&mpic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0xbfe>;
			fsl,descriptor-types-mask = <0x3ab0ebf>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		msi@41600 {
			compatible = "fsl,p1020-msi", "fsl,mpic-msi";
			reg = <0x41600 0x80>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
				0xe0 0
				0xe1 0
				0xe2 0
				0xe3 0
				0xe4 0
				0xe5 0
				0xe6 0
				0xe7 0>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities block
			compatible = "fsl,p1020-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};
	};

	pci0: pcie@ffe09000 {
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0 0xffe09000 0 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <16 2>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci1: pcie@ffe0a000 {
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0 0xffe0a000 0 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <16 2>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xc0000000
				  0x2000000 0x0 0xc0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};
};