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| author | Linux Build Service Account <lnxbuild@qualcomm.com> | 2010-07-01 18:08:42 -0700 |
|---|---|---|
| committer | QuIC Gerrit Code Review <code-review@quicinc.com> | 2010-07-01 18:08:42 -0700 |
| commit | 197e6330522f12b146968f7503c323f69962adaa (patch) | |
| tree | 5589114b5d43d5fdff08d4e8e5d3240d8f9f07a8 | |
| parent | 3896597f5631c5c9a639a7a8d830137e0b761803 (diff) | |
| parent | 738be4605e32d99c19b12f966fd76317c17b7d43 (diff) | |
| download | bionic-Q8650BSDCANLYA5015.zip bionic-Q8650BSDCANLYA5015.tar.gz bionic-Q8650BSDCANLYA5015.tar.bz2 | |
Merge changes I738be460,I46d5ba55 into froyoQ8650BSDCANLYA5015
* changes:
bionic: remove V5 instruction for V6 targets
bionic: Change cache line size to 32
| -rw-r--r-- | libc/arch-arm/bionic/memcpy.S | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/libc/arch-arm/bionic/memcpy.S b/libc/arch-arm/bionic/memcpy.S index ba55996..b8d1007 100644 --- a/libc/arch-arm/bionic/memcpy.S +++ b/libc/arch-arm/bionic/memcpy.S @@ -38,7 +38,7 @@ .align 4 /* a prefetch distance of 4 cache-lines works best experimentally */ -#define CACHE_LINE_SIZE 64 +#define CACHE_LINE_SIZE 32 #define PREFETCH_DISTANCE (CACHE_LINE_SIZE*4) memcpy: @@ -260,20 +260,31 @@ cached_aligned32: * */ +#if __ARM_ARCH__ == 5 // Align the preload register to a cache-line because the cpu does // "critical word first" (the first word requested is loaded first). bic r12, r1, #0x1F add r12, r12, #64 +#endif 1: ldmia r1!, { r4-r11 } + +#if __ARM_ARCH__ == 5 PLD (r12, #64) +#else + PLD (r1, #64) +#endif + subs r2, r2, #32 +#if __ARM_ARCH__ == 5 // NOTE: if r12 is more than 64 ahead of r1, the following ldrhi // for ARM9 preload will not be safely guarded by the preceding subs. // When it is safely guarded the only possibility to have SIGSEGV here // is because the caller overstates the length. ldrhi r3, [r12], #32 /* cheap ARM9 preload */ +#endif + stmia r0!, { r4-r11 } bhs 1b |