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author | thakis@chromium.org <thakis@chromium.org@0039d316-1c4b-4281-b951-d872f2087c98> | 2014-05-19 22:37:20 +0000 |
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committer | thakis@chromium.org <thakis@chromium.org@0039d316-1c4b-4281-b951-d872f2087c98> | 2014-05-19 22:37:20 +0000 |
commit | 3dd9f21718ea149dc06ad5a906a1d6dbe9f94dfd (patch) | |
tree | ffcd66f9810fe14604ca25c5c42eb409c18986c0 /base/atomicops_internals_x86_gcc.h | |
parent | bbd32301dd1f2c5075062583dfee835104bb3724 (diff) | |
download | chromium_src-3dd9f21718ea149dc06ad5a906a1d6dbe9f94dfd.zip chromium_src-3dd9f21718ea149dc06ad5a906a1d6dbe9f94dfd.tar.gz chromium_src-3dd9f21718ea149dc06ad5a906a1d6dbe9f94dfd.tar.bz2 |
base atomicops: Drop SSE2 detection, we always require SSE2 starting in m35.
BUG=348761,94925
NOTRY=true
Review URL: https://codereview.chromium.org/291993003
git-svn-id: svn://svn.chromium.org/chrome/trunk/src@271506 0039d316-1c4b-4281-b951-d872f2087c98
Diffstat (limited to 'base/atomicops_internals_x86_gcc.h')
-rw-r--r-- | base/atomicops_internals_x86_gcc.h | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/base/atomicops_internals_x86_gcc.h b/base/atomicops_internals_x86_gcc.h index ac02b17..7386fab 100644 --- a/base/atomicops_internals_x86_gcc.h +++ b/base/atomicops_internals_x86_gcc.h @@ -17,7 +17,6 @@ struct AtomicOps_x86CPUFeatureStruct { bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence // after acquire compare-and-swap. - bool has_sse2; // Processor has SSE2. }; BASE_EXPORT extern struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures; @@ -92,10 +91,6 @@ inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) { *ptr = value; } -#if defined(__x86_64__) - -// 64-bit implementations of memory barrier can be simpler, because it -// "mfence" is guaranteed to exist. inline void MemoryBarrier() { __asm__ __volatile__("mfence" : : : "memory"); } @@ -105,28 +100,6 @@ inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) { MemoryBarrier(); } -#else - -inline void MemoryBarrier() { - if (AtomicOps_Internalx86CPUFeatures.has_sse2) { - __asm__ __volatile__("mfence" : : : "memory"); - } else { // mfence is faster but not present on PIII - Atomic32 x = 0; - NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII - } -} - -inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) { - if (AtomicOps_Internalx86CPUFeatures.has_sse2) { - *ptr = value; - __asm__ __volatile__("mfence" : : : "memory"); - } else { - NoBarrier_AtomicExchange(ptr, value); - // acts as a barrier on PIII - } -} -#endif - inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) { ATOMICOPS_COMPILER_BARRIER(); *ptr = value; // An x86 store acts as a release barrier. |