[MIPS] Fix memory barriers for atomic operations.

Add barriers using MIPS 'sync' instructions as needed for SMP
systems.

BUG=246947

Review URL: https://chromiumcodereview.appspot.com/16001009

git-svn-id: svn://svn.chromium.org/chrome/trunk/src@204697 0039d316-1c4b-4281-b951-d872f2087c98

1 files changed, 5 insertions, 12 deletions

diff --git a/base/atomicops_internals_mips_gcc.h b/base/atomicops_internals_mips_gcc.h
index 505597e..29947b3 100644
--- a/base/atomicops_internals_mips_gcc.h
+++ b/base/atomicops_internals_mips_gcc.h
@@ -9,8 +9,6 @@
 #ifndef BASE_ATOMICOPS_INTERNALS_MIPS_GCC_H_
 #define BASE_ATOMICOPS_INTERNALS_MIPS_GCC_H_
 
-#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
-
 namespace base {
 namespace subtle {
 
@@ -90,9 +88,9 @@ inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
 
 inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
                                         Atomic32 increment) {
-  ATOMICOPS_COMPILER_BARRIER();
+  MemoryBarrier();
   Atomic32 res = NoBarrier_AtomicIncrement(ptr, increment);
-  ATOMICOPS_COMPILER_BARRIER();
+  MemoryBarrier();
   return res;
 }
 
@@ -105,19 +103,16 @@ inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
 inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
                                        Atomic32 old_value,
                                        Atomic32 new_value) {
-  ATOMICOPS_COMPILER_BARRIER();
   Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
-  ATOMICOPS_COMPILER_BARRIER();
+  MemoryBarrier();
   return res;
 }
 
 inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
                                        Atomic32 old_value,
                                        Atomic32 new_value) {
-  ATOMICOPS_COMPILER_BARRIER();
-  Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
-  ATOMICOPS_COMPILER_BARRIER();
-  return res;
+  MemoryBarrier();
+  return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
 }
 
 inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
@@ -156,6 +151,4 @@ inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
 } // namespace base::subtle
 } // namespace base
 
-#undef ATOMICOPS_COMPILER_BARRIER
-
 #endif  // BASE_ATOMICOPS_INTERNALS_MIPS_GCC_H_