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path: root/lib/CodeGen/MachineScheduler.cpp
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* Update aosp/master LLVM for rebase to r235153Pirama Arumuga Nainar2015-05-181-2/+2
* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-091-0/+11
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-10/+13
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-14/+29
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-268/+68
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-41/+41
* Update to LLVM 3.5a.Stephen Hines2014-04-241-963/+1317
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-0/+4
* Revert r194865 and r194874.Alexey Samsonov2013-11-181-4/+0
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-151-0/+4
* Pass LiveQueryResult by valueMatthias Braun2013-10-101-3/+5
* Comment typo.Andrew Trick2013-09-241-1/+1
* Allow subtarget selection of the default MachineScheduler and document the in...Andrew Trick2013-09-201-12/+22
* Rename ConvergingScheduler to GenericScheduler.Andrew Trick2013-09-191-63/+63
* Enable -misched-cyclicpath by default.Andrew Trick2013-09-091-1/+1
* mi-sched: smooth out the cyclicpath heuristic.Andrew Trick2013-09-091-1/+4
* mi-sched: cleanup register pressure update, remove a FIXME.Andrew Trick2013-09-061-19/+26
* mi-sched: improve regpressure tracing.Andrew Trick2013-09-061-2/+7
* mi-sched: print tree size in -view-misched-dagsAndrew Trick2013-09-061-1/+5
* mi-sched: register pressure update tracing.Andrew Trick2013-09-061-0/+4
* mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics.Andrew Trick2013-09-061-4/+4
* Added MachineSchedPolicy.Andrew Trick2013-09-061-35/+51
* mi-sched: Force bottom up scheduling for generic targets.Andrew Trick2013-09-041-3/+23
* comment typoAndrew Trick2013-09-041-1/+1
* Remove dead subtree limit code.Andrew Trick2013-09-041-9/+0
* -view-misched-dags, better pruning.Andrew Trick2013-09-041-1/+1
* mi-sched: DEBUG cleanup, call tracePick for unidirectional scheduling.Andrew Trick2013-09-041-0/+2
* 80 columnsAndrew Trick2013-09-041-2/+2
* mi-sched: Suppress register pressure tracking when the scheduling window is t...Andrew Trick2013-09-041-16/+29
* mi-sched: Load clustering is a bit to expensive to enable unconditionally.Andrew Trick2013-09-041-1/+1
* mi-sched: Reuse an invalid HazardRecognizer to save compile time.Andrew Trick2013-09-041-6/+14
* mi-sched: bypass heuristic checks when regpressure tracking is disabled.Andrew Trick2013-09-041-24/+29
* Added -misched-regpressure option.Andrew Trick2013-09-041-13/+31
* Fix my previous checkin to updatePressureDiffs.Andrew Trick2013-08-311-4/+19
* mi-sched: update PressureDiffs on-the-fly for liveness.Andrew Trick2013-08-301-5/+59
* mi-sched: improve the generic register pressure comparison.Andrew Trick2013-08-301-14/+12
* mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness...Andrew Trick2013-08-301-27/+51
* comment typoAndrew Trick2013-08-301-1/+1
* Comment and revise the cyclic critical path code.Andrew Trick2013-08-291-13/+116
* Adds cyclic critical path computation and heuristics, temporarily disabled.Andrew Trick2013-08-231-21/+68
* mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr c...Andrew Trick2013-08-231-5/+7
* Confusing comment typo.Andrew Trick2013-08-071-1/+1
* MI Sched: Track live-thru registers.Andrew Trick2013-07-301-2/+10
* MI Sched fix: assert "Disconnected LRG within the scheduling region."Andrew Trick2013-07-301-0/+6
* MI Sched: Register pressure heuristics.Andrew Trick2013-07-251-8/+32
* Dump LIS before regalloc. MI sched changes them.Andrew Trick2013-07-251-2/+2
* Fix uninitialized memory read found by MemorySanitizer: always set output par...Alexey Samsonov2013-07-191-1/+1
* MI Sched: Update the way resources are tracked so the current heuristics make...Andrew Trick2013-07-191-7/+5
* MI-Sched: cleanup DEBUG output.Andrew Trick2013-06-211-5/+6
* MI-Sched: Adjust regpressure limits for reserved regs.Andrew Trick2013-06-211-2/+3