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| author | Ralf Baechle <ralf@linux-mips.org> | 2005-08-16 15:44:06 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:32:02 +0100 |
| commit | 479a0e3e0245fa116412bc105ab1161636c220cb (patch) | |
| tree | 3aa73f8d4626f1f29821df184fa9d6df9d08e6d4 /arch/mips | |
| parent | fd0197d26208b896caa958cc1780e8016f439711 (diff) | |
| download | kernel_i9300_mainline-479a0e3e0245fa116412bc105ab1161636c220cb.zip kernel_i9300_mainline-479a0e3e0245fa116412bc105ab1161636c220cb.tar.gz kernel_i9300_mainline-479a0e3e0245fa116412bc105ab1161636c220cb.tar.bz2 | |
Support for CoreFPGA-3.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/mips-boards/generic/init.c | 1 | ||||
| -rw-r--r-- | arch/mips/mips-boards/generic/pci.c | 1 | ||||
| -rw-r--r-- | arch/mips/mips-boards/malta/malta_int.c | 21 |
3 files changed, 8 insertions, 15 deletions
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index 58256ea..eab5a70 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -337,6 +337,7 @@ void __init prom_init(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c index c8398c4..1f6f9df 100644 --- a/arch/mips/mips-boards/generic/pci.c +++ b/arch/mips/mips-boards/generic/pci.c @@ -197,6 +197,7 @@ void __init mips_pcibios_init(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: /* Set up resource ranges from the controller's registers. */ MSC_READ(MSC01_PCI_SC2PMBASL, start); diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c index 6f99a44..d06dc5ad 100644 --- a/arch/mips/mips-boards/malta/malta_int.c +++ b/arch/mips/mips-boards/malta/malta_int.c @@ -57,6 +57,7 @@ static inline int mips_pcibios_iack(void) switch(mips_revision_corid) { case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: MSC_READ(MSC01_PCI_IACK, irq); irq &= 0xff; @@ -103,22 +104,10 @@ static inline int get_int(void) irq = mips_pcibios_iack(); /* - * IRQ7 is used to detect spurious interrupts. - * The interrupt acknowledge cycle returns IRQ7, if no - * interrupts is requested. - * We can differentiate between this situation and a - * "Normal" IRQ7 by reading the ISR. + * The only way we can decide if an interrupt is spurious + * is by checking the 8259 registers. This needs a spinlock + * on an SMP system, so leave it up to the generic code... */ - if (irq == 7) - { - outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR, - PIIX4_ICTLR1_OCW3); - if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) { - irq = -1; /* Spurious interrupt */ - printk("We got a spurious interrupt from PIIX4.\n"); - atomic_inc(&irq_err_count); - } - } spin_unlock_irqrestore(&mips_irq_lock, flags); @@ -153,6 +142,7 @@ void corehi_irqdispatch(struct pt_regs *regs) switch(mips_revision_corid) { case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: ll_msc_irq(regs); break; @@ -233,6 +223,7 @@ void __init arch_init_irq(void) switch(mips_revision_corid) { case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: if (cpu_has_veic) init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); |