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| author | Adrian Bunk <bunk@stusta.de> | 2006-06-30 18:23:39 +0200 |
|---|---|---|
| committer | Adrian Bunk <bunk@stusta.de> | 2006-06-30 18:23:39 +0200 |
| commit | fd245f00695cbcf0f8430f35841c216559d243df (patch) | |
| tree | 20d1a5a98e5d626ce8215316b16c8cdf392995a7 | |
| parent | 0418726bb5c7b5a70c7e7e82e860d5979d0c78cf (diff) | |
| download | kernel_samsung_smdk4412-fd245f00695cbcf0f8430f35841c216559d243df.zip kernel_samsung_smdk4412-fd245f00695cbcf0f8430f35841c216559d243df.tar.gz kernel_samsung_smdk4412-fd245f00695cbcf0f8430f35841c216559d243df.tar.bz2 | |
typo fixes: disadvantadge -> disadvantage
Signed-off-by: Adrian Bunk <bunk@stusta.de>
| -rw-r--r-- | Documentation/arm/IXP4xx | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-ixp4xx/io.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/arm/IXP4xx b/Documentation/arm/IXP4xx index d4c6d3a..43edb4e 100644 --- a/Documentation/arm/IXP4xx +++ b/Documentation/arm/IXP4xx @@ -85,7 +85,7 @@ IXP4xx provides two methods of accessing PCI memory space: 2) If > 64MB of memory space is required, the IXP4xx can be configured to use indirect registers to access PCI This allows for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. - The disadvantadge of this is that every PCI access requires + The disadvantage of this is that every PCI access requires three local register accesses plus a spinlock, but in some cases the performance hit is acceptable. In addition, you cannot mmap() PCI devices in this case due to the indirect nature diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h index b59520e..0d51726 100644 --- a/include/asm-arm/arch-ixp4xx/io.h +++ b/include/asm-arm/arch-ixp4xx/io.h @@ -38,7 +38,7 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); * 2) If > 64MB of memory space is required, the IXP4xx can be configured * to use indirect registers to access PCI (as we do below for I/O * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff) - * of memory on the bus. The disadvantadge of this is that every + * of memory on the bus. The disadvantage of this is that every * PCI access requires three local register accesses plus a spinlock, * but in some cases the performance hit is acceptable. In addition, * you cannot mmap() PCI devices in this case. |