samsung update 1

1 files changed, 580 insertions, 0 deletions

diff --git a/arch/arm/mach-exynos/p10-gpio.c b/arch/arm/mach-exynos/p10-gpio.c
new file mode 100644
index 0000000..3e6c9d3
--- /dev/null
+++ b/arch/arm/mach-exynos/p10-gpio.c
@@ -0,0 +1,580 @@
+/*
+ *  linux/arch/arm/mach-exynos/p10-gpio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS - GPIO setting in set board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/serial_core.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/gpio-midas.h>
+#include <plat/cpu.h>
+#include <mach/pmu.h>
+
+struct gpio_init_data {
+	uint num;
+	uint cfg;
+	uint val;
+	uint pud;
+	uint drv;
+};
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config);
+
+/* this is sample code for p10 board */
+static struct gpio_init_data p10_init_gpios[] = {
+
+	/* BT_UART_RXD */
+	{EXYNOS5_GPA0(0), S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_UP},
+	/* BT_UART_TXD */
+	{EXYNOS5_GPA0(1), S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	/* BT_UART_CTS */
+	{EXYNOS5_GPA0(2), S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	/* BT_UART_RTS */
+	{EXYNOS5_GPA0(3), S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+
+	/* UART switch: configure as output */
+	{EXYNOS5_GPE0(5), S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+	/* USB switch: configure as output */
+	{EXYNOS5_GPH0(1), S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS5_GPB2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SDA_1.8V */
+	{EXYNOS5_GPB2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SCL_1.8V */
+
+	{EXYNOS5_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* DET_3.5 */
+	{EXYNOS5_GPX0(2), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_IRQ */
+
+	{EXYNOS5_GPX2(0), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_UP */
+	{EXYNOS5_GPX2(1), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_DOWN */
+	{EXYNOS5_GPX2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* ADC_INT */
+	{EXYNOS5_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKE */
+};
+
+/* Initialize gpio set in p10 board */
+void p10_config_gpio_table(void)
+{
+	u32 i, gpio;
+
+	printk(KERN_DEBUG "%s\n", __func__);
+
+	for (i = 0; i < ARRAY_SIZE(p10_init_gpios); i++) {
+		gpio = p10_init_gpios[i].num;
+		s3c_gpio_cfgpin(gpio, p10_init_gpios[i].cfg);
+		s3c_gpio_setpull(gpio, p10_init_gpios[i].pud);
+
+		if (p10_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+			gpio_set_value(gpio, p10_init_gpios[i].val);
+
+		s5p_gpio_set_drvstr(gpio, p10_init_gpios[i].drv);
+	}
+}
+
+/* this table only for p10 board */
+static unsigned int exynos5_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_UP},	/* BT_UART_RXD */
+	{EXYNOS4_GPA0(1),  S3C_GPIO_SLP_OUT1,
+		S3C_GPIO_PULL_NONE},	/* BT_UART_TXD */
+	{EXYNOS4_GPA0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* BT_UART_CTS */
+	{EXYNOS4_GPA0(3),  S3C_GPIO_SLP_OUT1,
+		S3C_GPIO_PULL_NONE},	/* BT_UART_RTS */
+	{EXYNOS4_GPA0(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* GPS_UART_RXD */
+	{EXYNOS4_GPA0(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* GPS_UART_TXD */
+	{EXYNOS4_GPA0(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* GPS_UART_CTS */
+	{EXYNOS4_GPA0(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* GPS_UART_RTS */
+
+	{EXYNOS4_GPA1(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* AP_RXD */
+	{EXYNOS4_GPA1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* AP_TXD */
+	{EXYNOS4_GPA1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* TSP_SDA_1.8V */
+	{EXYNOS4_GPA1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* TSP_SCL_1.8V */
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* AP_FLM_RXD */
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* AP_FLM_TXD */
+
+	{EXYNOS5_GPA2(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* CHG_SDA_1.8V */
+	{EXYNOS5_GPA2(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* CHG_SCL_1.8V */
+	{EXYNOS5_GPA2(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* AP_PMIC_SDA */
+	{EXYNOS5_GPA2(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* AP_PMIC_SCL */
+	{EXYNOS5_GPA2(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* 5M_SPI_CLK */
+	{EXYNOS5_GPA2(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* 5M_SPI_CS */
+	{EXYNOS5_GPA2(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* 5M_SPI_DI */
+	{EXYNOS5_GPA2(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* 5M_SPI_DO */
+
+	{EXYNOS5_GPB0(0),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* AP_CP_INT */
+	{EXYNOS5_GPB0(1),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CMC221_CPU_RST */
+	{EXYNOS5_GPB0(2),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CMC_SPI_CLK_REQ */
+	{EXYNOS5_GPB0(3),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPB0(4),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPB1(0),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* BARO_INT */
+	{EXYNOS5_GPB1(1),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPB1(2),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPB1(3),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPB1(4),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPB2(0),   S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* LCD_PWM_IN_1.8V */
+	{EXYNOS5_GPB2(1),   S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* MOTOR_PWM */
+	{EXYNOS5_GPB2(2),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* CODEC_SDA_1.8V */
+	{EXYNOS5_GPB2(3),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* CODEC_SCL_1.8V */
+
+	{EXYNOS5_GPB3(0),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MHL_DSDA_1.8V */
+	{EXYNOS5_GPB3(1),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MHL_DSCL_1.8V */
+	{EXYNOS5_GPB3(2),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* GSENSE_SDA_1.8V */
+	{EXYNOS5_GPB3(3),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/*  GSENSE_SCL_1.8V */
+
+	{EXYNOS5_GPC0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_CLK */
+	{EXYNOS5_GPC0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_CMD */
+	{EXYNOS5_GPC0(2),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* eMMC_EN */
+	{EXYNOS5_GPC0(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(0) */
+	{EXYNOS5_GPC0(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(1) */
+	{EXYNOS5_GPC0(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(2) */
+	{EXYNOS5_GPC0(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(3) */
+
+	{EXYNOS5_GPC1(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPC1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPC1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPC1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(4) */
+	{EXYNOS5_GPC1(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(5) */
+	{EXYNOS5_GPC1(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(6) */
+	{EXYNOS5_GPC1(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(7) */
+
+	{EXYNOS5_GPC2(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* T_FLASH_CLK */
+	{EXYNOS5_GPC2(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* T_FLASH_CMD */
+	{EXYNOS5_GPC2(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPC2(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* T_FLASH_D(0) */
+	{EXYNOS5_GPC2(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* T_FLASH_D(1) */
+	{EXYNOS5_GPC2(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* T_FLASH_D(2) */
+	{EXYNOS5_GPC2(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* T_FLASH_D(3) */
+
+	{EXYNOS5_GPC3(0),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* WLAN_SDIO_CLK */
+	{EXYNOS5_GPC3(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},		/* WLAN_SDIO_CMD */
+	{EXYNOS5_GPC3(2),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* OTG_EN */
+	{EXYNOS5_GPC3(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* WLAN_SDIO_D(0) */
+	{EXYNOS5_GPC3(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* WLAN_SDIO_D(1) */
+	{EXYNOS5_GPC3(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* WLAN_SDIO_D(2) */
+	{EXYNOS5_GPC3(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* WLAN_SDIO_D(3) */
+
+	{EXYNOS5_GPD0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* FUEL_SDA_1.8V */
+	{EXYNOS5_GPD0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* FUEL_SCL_1.8V */
+	{EXYNOS5_GPD0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* BSENSE_SDA_1.8V */
+	{EXYNOS5_GPD0(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* BSENSE_SCL_1.8V */
+	{EXYNOS5_GPD0(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MHL_SDA_1.8V */
+	{EXYNOS5_GPD0(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MHL_SCL_1.8V */
+	{EXYNOS5_GPD0(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* LCDP_SCL__1.8V */
+	{EXYNOS5_GPD0(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* LCDP_SDA__1.8V */
+
+	{EXYNOS5_GPD1(0),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* HDMI_EN */
+	{EXYNOS5_GPD1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPD1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MOTOR_SDA_1.8V */
+	{EXYNOS5_GPD1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MOTOR_SCL_1.8V */
+	{EXYNOS5_GPD1(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* LCD_ID */
+	{EXYNOS5_GPD1(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CMC_PMIC_PWRON */
+	{EXYNOS5_GPD1(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NFC_EN, NC */
+	{EXYNOS5_GPD1(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NFC_FIRMWARE, NC */
+
+	{EXYNOS5_GPE0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CIS_nRST */
+	{EXYNOS5_GPE0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* CHG_SDA_1.8V */
+	{EXYNOS5_GPE0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* CHG_SCL_1.8V */
+	{EXYNOS5_GPE0(3),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* PDA_ACTIVE */
+	{EXYNOS5_GPE0(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* ACCESSORY_CHECK */
+	{EXYNOS5_GPE0(5),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* UART_SEL */
+	{EXYNOS5_GPE0(6),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* GPS_nRST */
+	{EXYNOS5_GPE0(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* ISP_TXD */
+
+	{EXYNOS5_GPE1(0),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* GPS_EN */
+	{EXYNOS5_GPE1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* ISP_RXD */
+
+	{EXYNOS5_GPF0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* 5M_CAM_SDA_1.8V */
+	{EXYNOS5_GPF0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* 5M_CAM_SCL_1.8V */
+	{EXYNOS5_GPF0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* VT_CAM_SDA_1.8V */
+	{EXYNOS5_GPF0(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* VT_CAM_SCL_1.8V */
+
+	{EXYNOS5_GPF1(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPF1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPF1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPF1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPG0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* ALS_SDA_1.8V */
+	{EXYNOS5_GPG0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/*ALS_SCL_1.8V */
+	{EXYNOS5_GPG0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* USB3.0_EN */
+	{EXYNOS5_GPG0(3),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* FM34_PWDN */
+	{EXYNOS5_GPG0(4),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* FM34_RESET */
+	{EXYNOS5_GPG0(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* MHL_INT */
+	{EXYNOS5_GPG0(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* MHL_RST */
+
+	{EXYNOS5_GPG1(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CAM_FLASH_EN */
+	{EXYNOS5_GPG1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CAM_FLASH_SET */
+	{EXYNOS5_GPG1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* TOUCH_CHG */
+	{EXYNOS5_GPG1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* TOUCH_RESET */
+	{EXYNOS5_GPG1(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* TA_nCHG */
+	{EXYNOS5_GPG1(5),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* TA_EN */
+	{EXYNOS5_GPG1(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CAM_VT_nRST */
+	{EXYNOS5_GPG1(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPG2(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPG2(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* VTCAM_MCLK */
+
+	{EXYNOS5_GPH0(0),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* WLAN_EN */
+	{EXYNOS5_GPH0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* USB_SEL1 */
+	{EXYNOS5_GPH0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPH0(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CAM_MCLK */
+
+	{EXYNOS5_GPH1(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPH1(1),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* CODEC_LDO_EN */
+	{EXYNOS5_GPH1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* LIGHT_nINT */
+	{EXYNOS5_GPH1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* BT_WAKE */
+	{EXYNOS5_GPH1(4),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* FM34_BYPASS */
+	{EXYNOS5_GPH1(5),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* ACCESSORY_EN */
+	{EXYNOS5_GPH1(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPH1(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* LCD_EN */
+
+	{EXYNOS5_GPV0(0),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* BUCK4_SEL */
+	{EXYNOS5_GPV0(1),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* BUCK3_SEL */
+	{EXYNOS5_GPV0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* 5M_CORE_EN */
+	{EXYNOS5_GPV0(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CAM_IO_EN */
+	{EXYNOS5_GPV0(4),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* BUCK2_SEL */
+	{EXYNOS5_GPV0(5),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* PMIC_DVS3 */
+	{EXYNOS5_GPV0(6),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* PMIC_DVS2 */
+	{EXYNOS5_GPV0(7),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* PMIC_DVS1 */
+
+	{EXYNOS5_GPV1(0),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* WLAN_WAKE */
+	{EXYNOS5_GPV1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* HW_REV3 */
+	{EXYNOS5_GPV1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* HW_REV2 */
+	{EXYNOS5_GPV1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* HW_REV1 */
+	{EXYNOS5_GPV1(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* HW_REV0 */
+	{EXYNOS5_GPV1(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV1(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV1(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPV2(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV2(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV2(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV2(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV2(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* HUM_SCL_1.8V */
+	{EXYNOS5_GPV2(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* HUM_SDA_1.8V */
+	{EXYNOS5_GPV2(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MSENSE_SCL_1.8V */
+	{EXYNOS5_GPV2(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MSENSE_SDA_1.8V */
+
+	{EXYNOS5_GPV3(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* ADC_SCL_1.8V */
+	{EXYNOS5_GPV3(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* ADC_SDA_1.8V */
+	{EXYNOS5_GPV3(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV3(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV3(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV3(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV3(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV3(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPY0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_CSN */
+	{EXYNOS5_GPY0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY0(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY0(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_REN */
+	{EXYNOS5_GPY0(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_WEN */
+
+	{EXYNOS5_GPY1(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPY2(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* TF_EN */
+	{EXYNOS5_GPY2(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY2(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY2(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY2(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY2(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPY3(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(0) */
+	{EXYNOS5_GPY3(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(1) */
+	{EXYNOS5_GPY3(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(2) */
+	{EXYNOS5_GPY3(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(3) */
+	{EXYNOS5_GPY3(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(4) */
+	{EXYNOS5_GPY3(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(5) */
+	{EXYNOS5_GPY3(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(6) */
+	{EXYNOS5_GPY3(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(7) */
+
+	{EXYNOS5_GPY4(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(8) */
+	{EXYNOS5_GPY4(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(9) */
+	{EXYNOS5_GPY4(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(10) */
+	{EXYNOS5_GPY4(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(11) */
+	{EXYNOS5_GPY4(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(12) */
+	{EXYNOS5_GPY4(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(13) */
+	{EXYNOS5_GPY4(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY4(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPY5(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(0) */
+	{EXYNOS5_GPY5(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(1) */
+	{EXYNOS5_GPY5(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(2) */
+	{EXYNOS5_GPY5(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(3) */
+	{EXYNOS5_GPY5(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(4) */
+	{EXYNOS5_GPY5(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(5) */
+	{EXYNOS5_GPY5(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(6) */
+	{EXYNOS5_GPY5(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(7) */
+
+	{EXYNOS5_GPY6(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(8) */
+	{EXYNOS5_GPY6(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(9) */
+	{EXYNOS5_GPY6(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(10) */
+	{EXYNOS5_GPY6(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(11) */
+	{EXYNOS5_GPY6(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(12) */
+	{EXYNOS5_GPY6(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(13) */
+	{EXYNOS5_GPY6(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(14) */
+	{EXYNOS5_GPY6(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(15) */
+
+	{EXYNOS5_GPZ(0),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* MM_I2S_CLK */
+	{EXYNOS5_GPZ(1),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPZ(2),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* MM_I2S_SYNC */
+	{EXYNOS5_GPZ(3),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* MM_I2S_DI */
+	{EXYNOS5_GPZ(4),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* MM_I2S_DO */
+	{EXYNOS5_GPZ(5),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPZ(6),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+};
+
+static void config_sleep_gpio_table(int array_size,
+				    unsigned int (*gpio_table)[3])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]);
+		s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]);
+	}
+}
+
+/* To save power consumption, gpio pin set before enterling sleep */
+void p10_config_sleep_gpio_table(void)
+{
+	config_sleep_gpio_table(ARRAY_SIZE(exynos5_sleep_gpio_table),
+			exynos5_sleep_gpio_table);
+}