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| author | David Brown <davidb@codeaurora.org> | 2011-01-07 10:20:49 -0800 |
|---|---|---|
| committer | David Brown <davidb@codeaurora.org> | 2011-01-21 15:27:50 -0800 |
| commit | 8c27e6f305242ffab0c88eed5dea8394b8ce86d0 (patch) | |
| tree | 1fdcfc10f74a18883848b7273edd9f7e01cbcefe /arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | |
| parent | 87fa28e972c223f69c1315a1b2ddb2a11d33ad0e (diff) | |
| download | kernel_samsung_smdk4412-8c27e6f305242ffab0c88eed5dea8394b8ce86d0.zip kernel_samsung_smdk4412-8c27e6f305242ffab0c88eed5dea8394b8ce86d0.tar.gz kernel_samsung_smdk4412-8c27e6f305242ffab0c88eed5dea8394b8ce86d0.tar.bz2 | |
msm: Generalize timer register mappings
Allow the timer register to be determined dynamically instead of at
compile time. Use common virtual addresses for the registers across
all MSM chips, and select the register mappings based on the detected
CPU.
Signed-off-by: David Brown <davidb@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm/include/mach/msm_iomap-8x50.h')
| -rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | 14 |
1 files changed, 3 insertions, 11 deletions
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index acc819e..cf1c2df 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved. * Author: Brian Swetland <swetland@google.com> * * This software is licensed under the terms of the GNU General Public @@ -39,16 +39,8 @@ #define MSM_VIC_PHYS 0xAC000000 #define MSM_VIC_SIZE SZ_4K -#define MSM_CSR_BASE IOMEM(0xE0001000) -#define MSM_CSR_PHYS 0xAC100000 -#define MSM_CSR_SIZE SZ_4K - -#define MSM_TMR_PHYS MSM_CSR_PHYS -#define MSM_TMR_BASE MSM_CSR_BASE -#define MSM_TMR_SIZE SZ_4K - -#define MSM_GPT_BASE MSM_TMR_BASE -#define MSM_DGT_BASE (MSM_TMR_BASE + 0x10) +#define QSD8X50_CSR_PHYS 0xAC100000 +#define QSD8X50_CSR_SIZE SZ_4K #define MSM_DMOV_BASE IOMEM(0xE0002000) #define MSM_DMOV_PHYS 0xA9700000 |