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| author | Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> | 2009-10-22 14:47:42 -0700 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2009-10-22 14:47:42 -0700 |
| commit | c33da3a80074094303d643a90ef589330b491270 (patch) | |
| tree | 64c8a0d9a56a4590e21641c04deae0b6a66eb8c0 /arch/arm/mach-omap1/serial.c | |
| parent | dcc730dc9d7614fdaf6bce73d6e8ffe47c8820b1 (diff) | |
| download | kernel_samsung_smdk4412-c33da3a80074094303d643a90ef589330b491270.zip kernel_samsung_smdk4412-c33da3a80074094303d643a90ef589330b491270.tar.gz kernel_samsung_smdk4412-c33da3a80074094303d643a90ef589330b491270.tar.bz2 | |
omap1: Fix redundant UARTs pin muxing that can break other hardware support
Commit 15ac408ee5a509053a765b816e9179515329369f removed enabled_uart
and OMAP_TAG_UART. This works for mach-omap2, but causes issues on
mach-omap1 for some boards as the mach-omap1 serial.c was muxing
pins based on the enabled_uart flag for 15xx.
Fix this by muxing pins in board-*.c files for the 15xx boards for
the uart ports that had enabled_uart flag set before the commit
above.
Tested on Amsdtrad Delta only.
Note that in the future we should add support for powering down
the uarts with a timer like mach-omap2/serial.c does. Otherwise
the enabled uarts will be blocking retention-while-idle.
Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap1/serial.c')
| -rw-r--r-- | arch/arm/mach-omap1/serial.c | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index d496e50..d23979b 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -131,8 +131,6 @@ void __init omap_serial_init(void) } for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { - unsigned char reg; - switch (i) { case 0: uart1_ck = clk_get(NULL, "uart1_ck"); @@ -143,16 +141,6 @@ void __init omap_serial_init(void) if (cpu_is_omap15xx()) clk_set_rate(uart1_ck, 12000000); } - if (cpu_is_omap15xx()) { - omap_cfg_reg(UART1_TX); - omap_cfg_reg(UART1_RTS); - if (machine_is_omap_innovator()) { - reg = fpga_read(OMAP1510_FPGA_POWER); - reg |= OMAP1510_FPGA_PCR_COM1_EN; - fpga_write(reg, OMAP1510_FPGA_POWER); - udelay(10); - } - } break; case 1: uart2_ck = clk_get(NULL, "uart2_ck"); @@ -165,16 +153,6 @@ void __init omap_serial_init(void) else clk_set_rate(uart2_ck, 48000000); } - if (cpu_is_omap15xx()) { - omap_cfg_reg(UART2_TX); - omap_cfg_reg(UART2_RTS); - if (machine_is_omap_innovator()) { - reg = fpga_read(OMAP1510_FPGA_POWER); - reg |= OMAP1510_FPGA_PCR_COM2_EN; - fpga_write(reg, OMAP1510_FPGA_POWER); - udelay(10); - } - } break; case 2: uart3_ck = clk_get(NULL, "uart3_ck"); @@ -185,10 +163,6 @@ void __init omap_serial_init(void) if (cpu_is_omap15xx()) clk_set_rate(uart3_ck, 12000000); } - if (cpu_is_omap15xx()) { - omap_cfg_reg(UART3_TX); - omap_cfg_reg(UART3_RX); - } break; } omap_serial_reset(&serial_platform_data[i]); |