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| author | Chris Metcalf <cmetcalf@tilera.com> | 2010-08-13 19:59:15 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2010-08-13 19:59:15 -0400 |
| commit | 7d72e6fa56c4100b9669efe0044f77ed9eb785a1 (patch) | |
| tree | 5e90bf4969809a1ab20b97432b85be20ccfaa1f4 /arch/arm/mach-s3c64xx/clock.c | |
| parent | ba00376b0b13f234d839541a7b36a5bf5c2a4036 (diff) | |
| parent | 2be1f3a73dd02e38e181cf5abacb3d45a6a2d6b8 (diff) | |
| download | kernel_samsung_smdk4412-7d72e6fa56c4100b9669efe0044f77ed9eb785a1.zip kernel_samsung_smdk4412-7d72e6fa56c4100b9669efe0044f77ed9eb785a1.tar.gz kernel_samsung_smdk4412-7d72e6fa56c4100b9669efe0044f77ed9eb785a1.tar.bz2 | |
Merge branch 'master' into for-linus
Diffstat (limited to 'arch/arm/mach-s3c64xx/clock.c')
| -rw-r--r-- | arch/arm/mach-s3c64xx/clock.c | 24 |
1 files changed, 18 insertions, 6 deletions
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index fbd85a9..7e03f0a 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -133,6 +133,12 @@ static struct clk init_clocks_disable[] = { .id = -1, .parent = &clk_h, }, { + .name = "rtc", + .id = -1, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_RTC, + }, { .name = "adc", .id = -1, .parent = &clk_p, @@ -165,6 +171,12 @@ static struct clk init_clocks_disable[] = { .ctrlbit = S3C6410_CLKCON_PCLK_IIS2, }, { #endif + .name = "keypad", + .id = -1, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, + }, { .name = "spi", .id = 0, .parent = &clk_p, @@ -295,12 +307,6 @@ static struct clk init_clocks[] = { .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_UART3, }, { - .name = "rtc", - .id = -1, - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_RTC, - }, { .name = "watchdog", .id = -1, .parent = &clk_p, @@ -310,6 +316,12 @@ static struct clk init_clocks[] = { .id = -1, .parent = &clk_p, .ctrlbit = S3C_CLKCON_PCLK_AC97, + }, { + .name = "cfcon", + .id = -1, + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_IHOST, } }; |