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| author | Yi Li <yi.li@analog.com> | 2009-01-07 23:14:39 +0800 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2009-01-07 23:14:39 +0800 |
| commit | 6a01f230339321292cf065551f8cf55361052461 (patch) | |
| tree | 7ac2ac8fc9f05a7315ef6a7f6f0a387433c62c14 /arch/blackfin/mach-bf537/include | |
| parent | 5105432a3201e3f0e6c219cd0a74feee1e5e262b (diff) | |
| download | kernel_samsung_smdk4412-6a01f230339321292cf065551f8cf55361052461.zip kernel_samsung_smdk4412-6a01f230339321292cf065551f8cf55361052461.tar.gz kernel_samsung_smdk4412-6a01f230339321292cf065551f8cf55361052461.tar.bz2 | |
Blackfin arch: merge adeos blackfin part to arch/blackfin/
[Mike Frysinger <vapier.adi@gmail.com>:
- handle bf531/bf532/bf534/bf536 variants in ipipe.h
- cleanup IPIPE logic for bfin_set_irq_handler()
- cleanup ipipe asm code a bit and add missing ENDPROC()
- simplify IPIPE code in trap_c
- unify some of the IPIPE code and fix style
- simplify DO_IRQ_L1 handling with ipipe code
- revert IRQ_SW_INT# addition from ipipe merge
- remove duplicate get_{c,s}clk() prototypes
]
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf537/include')
| -rw-r--r-- | arch/blackfin/mach-bf537/include/mach/cdefBF534.h | 8 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf537/include/mach/irq.h | 32 |
2 files changed, 20 insertions, 20 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h index f341692..5f8b5f8 100644 --- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h @@ -1783,7 +1783,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val) if (val == bfin_read_PLL_CTL()) return; - local_irq_save(flags); + local_irq_save_hw(flags); /* Enable the PLL Wakeup bit in SIC IWR */ iwr = bfin_read32(SIC_IWR); /* Only allow PPL Wakeup) */ @@ -1794,7 +1794,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val) asm("IDLE;"); bfin_write32(SIC_IWR, iwr); - local_irq_restore(flags); + local_irq_restore_hw(flags); } /* Writing to VR_CTL initiates a PLL relock sequence. */ @@ -1805,7 +1805,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) if (val == bfin_read_VR_CTL()) return; - local_irq_save(flags); + local_irq_save_hw(flags); /* Enable the PLL Wakeup bit in SIC IWR */ iwr = bfin_read32(SIC_IWR); /* Only allow PPL Wakeup) */ @@ -1816,7 +1816,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) asm("IDLE;"); bfin_write32(SIC_IWR, iwr); - local_irq_restore(flags); + local_irq_restore_hw(flags); } #endif /* _CDEF_BF534_H */ diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h index 2e68a8a..b2a71d5 100644 --- a/arch/blackfin/mach-bf537/include/mach/irq.h +++ b/arch/blackfin/mach-bf537/include/mach/irq.h @@ -82,14 +82,14 @@ #define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */ #define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */ #define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */ -#define IRQ_TMR0 26 /*Timer 0 */ -#define IRQ_TMR1 27 /*Timer 1 */ -#define IRQ_TMR2 28 /*Timer 2 */ -#define IRQ_TMR3 29 /*Timer 3 */ -#define IRQ_TMR4 30 /*Timer 4 */ -#define IRQ_TMR5 31 /*Timer 5 */ -#define IRQ_TMR6 32 /*Timer 6 */ -#define IRQ_TMR7 33 /*Timer 7 */ +#define IRQ_TIMER0 26 /*Timer 0 */ +#define IRQ_TIMER1 27 /*Timer 1 */ +#define IRQ_TIMER2 28 /*Timer 2 */ +#define IRQ_TIMER3 29 /*Timer 3 */ +#define IRQ_TIMER4 30 /*Timer 4 */ +#define IRQ_TIMER5 31 /*Timer 5 */ +#define IRQ_TIMER6 32 /*Timer 6 */ +#define IRQ_TIMER7 33 /*Timer 7 */ #define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */ #define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ #define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ @@ -195,16 +195,16 @@ #define IRQ_CAN_TX_POS 0 #define IRQ_MAC_RX_POS 4 #define IRQ_MAC_TX_POS 8 -#define IRQ_TMR0_POS 12 -#define IRQ_TMR1_POS 16 -#define IRQ_TMR2_POS 20 -#define IRQ_TMR3_POS 24 -#define IRQ_TMR4_POS 28 +#define IRQ_TIMER0_POS 12 +#define IRQ_TIMER1_POS 16 +#define IRQ_TIMER2_POS 20 +#define IRQ_TIMER3_POS 24 +#define IRQ_TIMER4_POS 28 /* IAR3 BIT FIELDS*/ -#define IRQ_TMR5_POS 0 -#define IRQ_TMR6_POS 4 -#define IRQ_TMR7_POS 8 +#define IRQ_TIMER5_POS 0 +#define IRQ_TIMER6_POS 4 +#define IRQ_TIMER7_POS 8 #define IRQ_PROG_INTA_POS 12 #define IRQ_PORTG_INTB_POS 16 #define IRQ_MEM_DMA0_POS 20 |