diff options
| author | Ingo Molnar <mingo@elte.hu> | 2009-01-18 20:15:05 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-01-18 20:15:05 +0100 |
| commit | 4092762aebfe55c1f8e31440b80a053c2dbe519b (patch) | |
| tree | 8fb9fd14131194174c12daf5d8195afd3b62bc3e /arch/mips/include/asm/mipsregs.h | |
| parent | 745b1626dd71ce9661a05ea4db57859ed5c773d2 (diff) | |
| parent | 1de9e8e70f5acc441550ca75433563d91b269bbe (diff) | |
| download | kernel_samsung_smdk4412-4092762aebfe55c1f8e31440b80a053c2dbe519b.zip kernel_samsung_smdk4412-4092762aebfe55c1f8e31440b80a053c2dbe519b.tar.gz kernel_samsung_smdk4412-4092762aebfe55c1f8e31440b80a053c2dbe519b.tar.bz2 | |
Merge branch 'tracing/ftrace'; commit 'v2.6.29-rc2' into tracing/core
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 9316324..0417516 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1000,6 +1000,26 @@ do { \ #define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) + +/* Cavium OCTEON (cnMIPS) */ +#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) +#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) + +#define read_c0_cvmctl() __read_64bit_c0_register($9, 7) +#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) + +#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) +#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) +/* + * The cacheerr registers are not standardized. On OCTEON, they are + * 64 bits wide. + */ +#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) +#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) + +#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) +#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) + /* * Macros to access the floating point coprocessor control registers */ @@ -1008,6 +1028,8 @@ do { \ __asm__ __volatile__( \ ".set\tpush\n\t" \ ".set\treorder\n\t" \ + /* gas fails to assemble cfc1 for some archs (octeon).*/ \ + ".set\tmips1\n\t" \ "cfc1\t%0,"STR(source)"\n\t" \ ".set\tpop" \ : "=r" (__res)); \ |