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| author | Deng-Cheng Zhu <dengcheng.zhu@gmail.com> | 2010-10-12 19:37:21 +0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-10-29 19:08:48 +0100 |
| commit | 7f788d2d53085815d474559cd51ef1f38b0a9bb8 (patch) | |
| tree | 32c2b6af15da818a02502a678225ff4de754b542 /arch/mips/math-emu | |
| parent | 6dbd972850c092e50e10bd14a3324e2abe88997a (diff) | |
| download | kernel_samsung_smdk4412-7f788d2d53085815d474559cd51ef1f38b0a9bb8.zip kernel_samsung_smdk4412-7f788d2d53085815d474559cd51ef1f38b0a9bb8.tar.gz kernel_samsung_smdk4412-7f788d2d53085815d474559cd51ef1f38b0a9bb8.tar.bz2 | |
MIPS: add support for software performance events
Software events are required as part of the measurable stuff by the
Linux performance counter subsystem. Here is the list of events added by
this patch:
PERF_COUNT_SW_PAGE_FAULTS
PERF_COUNT_SW_PAGE_FAULTS_MIN
PERF_COUNT_SW_PAGE_FAULTS_MAJ
PERF_COUNT_SW_ALIGNMENT_FAULTS
PERF_COUNT_SW_EMULATION_FAULTS
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
To: linux-mips@linux-mips.org
Cc: a.p.zijlstra@chello.nl
Cc: paulus@samba.org
Cc: mingo@elte.hu
Cc: acme@redhat.com
Cc: jamie.iles@picochip.com
Acked-by: David Daney <ddaney@caviumnetworks.com>
Reviewed-by: Matt Fleming <matt@console-pimps.org>
Patchwork: https://patchwork.linux-mips.org/patch/1686/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/math-emu')
| -rw-r--r-- | arch/mips/math-emu/cp1emu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index ec3faa4..b2ad1b0 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -36,6 +36,7 @@ #include <linux/sched.h> #include <linux/module.h> #include <linux/debugfs.h> +#include <linux/perf_event.h> #include <asm/inst.h> #include <asm/bootinfo.h> @@ -258,6 +259,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) } emul: + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, + 1, 0, xcp, 0); MIPS_FPU_EMU_INC_STATS(emulated); switch (MIPSInst_OPCODE(ir)) { case ldc1_op:{ |