diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2010-10-15 02:13:04 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-10-15 02:13:04 +0900 |
| commit | d8d6b902b8a3b2c66151529694bb4a9a3555cf43 (patch) | |
| tree | e2ab4dff9888dc2cd0998299959bfa5b9409cdd5 /arch/sh/include | |
| parent | c993487ec87ba6d9ea47b03dad562123d503f4a2 (diff) | |
| download | kernel_samsung_smdk4412-d8d6b902b8a3b2c66151529694bb4a9a3555cf43.zip kernel_samsung_smdk4412-d8d6b902b8a3b2c66151529694bb4a9a3555cf43.tar.gz kernel_samsung_smdk4412-d8d6b902b8a3b2c66151529694bb4a9a3555cf43.tar.bz2 | |
sh: mach-sdk7786: Add support for the FPGA SRAM.
This ties in the 2KiB of FPGA SRAM in to the generic SRAM pool.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include')
| -rw-r--r-- | arch/sh/include/asm/sizes.h | 1 | ||||
| -rw-r--r-- | arch/sh/include/mach-sdk7786/mach/fpga.h | 17 |
2 files changed, 17 insertions, 1 deletions
diff --git a/arch/sh/include/asm/sizes.h b/arch/sh/include/asm/sizes.h index 3a1fb97..0b9fe2d 100644 --- a/arch/sh/include/asm/sizes.h +++ b/arch/sh/include/asm/sizes.h @@ -32,6 +32,7 @@ #define SZ_512 0x00000200 #define SZ_1K 0x00000400 +#define SZ_2K 0x00000800 #define SZ_4K 0x00001000 #define SZ_8K 0x00002000 #define SZ_16K 0x00004000 diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h index b7d9369..40f0c2d 100644 --- a/arch/sh/include/mach-sdk7786/mach/fpga.h +++ b/arch/sh/include/mach-sdk7786/mach/fpga.h @@ -43,8 +43,23 @@ #define FAER 0x150 #define USRGPIR 0x160 + /* 0x170 reserved */ -#define LCLASR 0x180 + +#define LCLASR 0x180 +#define LCLASR_FRAMEN BIT(15) + +#define LCLASR_FPGA_SEL_SHIFT 12 +#define LCLASR_NAND_SEL_SHIFT 8 +#define LCLASR_NORB_SEL_SHIFT 4 +#define LCLASR_NORA_SEL_SHIFT 0 + +#define LCLASR_AREA_MASK 0x7 + +#define LCLASR_FPGA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT) +#define LCLASR_NAND_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT) +#define LCLASR_NORB_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT) +#define LCLASR_NORA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT) #define SBCR 0x190 #define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */ |