diff options
| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2009-03-23 18:07:49 -0700 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2009-03-23 18:51:20 -0700 |
| commit | 52176e70837d56cd238d6edc04cc403f1ffa86c6 (patch) | |
| tree | 2904080fdc840989a0cea9c9dff340398b6e24cb /arch | |
| parent | 2263f0222e836c7b2c144e0546a2701661e2f517 (diff) | |
| download | kernel_samsung_smdk4412-52176e70837d56cd238d6edc04cc403f1ffa86c6.zip kernel_samsung_smdk4412-52176e70837d56cd238d6edc04cc403f1ffa86c6.tar.gz kernel_samsung_smdk4412-52176e70837d56cd238d6edc04cc403f1ffa86c6.tar.bz2 | |
ARM: OMAP: Dispatch only relevant DMA interrupts
This fixes the spurious interrupt issue on a DMA channel.
In OMAP sDMA, contrast to the SDMA.DMA4_CSRi registers, the
SDMA.DMA4_IRQSTATUS_Lj registers are updated regardless of
the corresponding bits in the SDMA.DMA4_IRQENABLE_Lj registers.
Since there are four sDMA interrupt lines and if more than one
line is actively used by two concurrently running sDMA softwares
modules,then the spurious interrupt can be observed on the other
lines.
Fix in this patch will only dispatch the relevant and enabled
interrupts on a particular line thus perevting spurious IRQ.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Nishant Kamat <nskamat@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/plat-omap/dma.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index b1d3c79..21cc014 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1901,7 +1901,7 @@ static int omap2_dma_handle_ch(int ch) /* STATUS register count is from 1-32 while our is 0-31 */ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) { - u32 val; + u32 val, enable_reg; int i; val = dma_read(IRQSTATUS_L0); @@ -1910,6 +1910,8 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) printk(KERN_WARNING "Spurious DMA IRQ\n"); return IRQ_HANDLED; } + enable_reg = dma_read(IRQENABLE_L0); + val &= enable_reg; /* Dispatch only relevant interrupts */ for (i = 0; i < dma_lch_count && val != 0; i++) { if (val & 1) omap2_dma_handle_ch(i); |