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| author | venkatesh.pallipadi@intel.com <venkatesh.pallipadi@intel.com> | 2008-08-20 16:45:53 -0700 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-08-21 13:27:34 +0200 |
| commit | 8323444b5dba3fe55e56a95d20d8f55c1d6745af (patch) | |
| tree | e2d657ff43c768d3b9f47642fa522cba1c3ffcd8 /arch | |
| parent | 28df82ebab79c6a2b4295dd94fd8de88196a49df (diff) | |
| download | kernel_samsung_smdk4412-8323444b5dba3fe55e56a95d20d8f55c1d6745af.zip kernel_samsung_smdk4412-8323444b5dba3fe55e56a95d20d8f55c1d6745af.tar.gz kernel_samsung_smdk4412-8323444b5dba3fe55e56a95d20d8f55c1d6745af.tar.bz2 | |
x86: PAT Update validate_pat_support for intel CPUs
Pentium III and Core Solo/Duo CPUs have an erratum
" Page with PAT set to WC while associated MTRR is UC may consolidate to UC "
which can result in WC setting in PAT to be ineffective. We will disable
PAT on such CPUs, so that we can continue to use MTRR WC setting.
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/kernel/cpu/addon_cpuid_features.c | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/addon_cpuid_features.c index 84a8220..a6ef672 100644 --- a/arch/x86/kernel/cpu/addon_cpuid_features.c +++ b/arch/x86/kernel/cpu/addon_cpuid_features.c @@ -56,9 +56,22 @@ void __cpuinit validate_pat_support(struct cpuinfo_x86 *c) switch (c->x86_vendor) { case X86_VENDOR_INTEL: - if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15)) + /* + * There is a known erratum on Pentium III and Core Solo + * and Core Duo CPUs. + * " Page with PAT set to WC while associated MTRR is UC + * may consolidate to UC " + * Because of this erratum, it is better to stick with + * setting WC in MTRR rather than using PAT on these CPUs. + * + * Enable PAT WC only on P4, Core 2 or later CPUs. + */ + if (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 15)) return; - break; + + pat_disable("PAT WC disabled due to known CPU erratum."); + return; + case X86_VENDOR_AMD: case X86_VENDOR_CENTAUR: case X86_VENDOR_TRANSMETA: |