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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-06-29 13:34:36 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-11-21 14:31:20 -0800 |
| commit | 987ccebc15b3f1256dbcdfbb81ad542d1e2ad6a8 (patch) | |
| tree | 8698201286d0a4f38a0323dfec5f70865b8ff6b3 /drivers/gpu/drm/i915/i915_debugfs.c | |
| parent | efd5ea63c5632e2365373458e013e2d4d0fc73ac (diff) | |
| download | kernel_samsung_smdk4412-987ccebc15b3f1256dbcdfbb81ad542d1e2ad6a8.zip kernel_samsung_smdk4412-987ccebc15b3f1256dbcdfbb81ad542d1e2ad6a8.tar.gz kernel_samsung_smdk4412-987ccebc15b3f1256dbcdfbb81ad542d1e2ad6a8.tar.bz2 | |
drm/i915: enable ring freq scaling, RC6 and graphics turbo on Ivy Bridge v3
commit 1c70c0cebd1295a42fec75045b8a6b4419cedef3 upstream.
They use the same register interfaces, so we can simply enable the
existing code on IVB.
v2:
- resolve conflict with ring freq scaling, we can enable it too
v3:
- resolve conflict again, this time on drm-intel-next
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Robert Hooker <robert.hooker@canonical.com>
Acked-by: Leann Ogasawara <leann.ogasawara@canonical.com>
Acked-by: Herton Krzesinski <herton.krzesinski@canonical.com>
Signed-off-by: Tim Gardner <tim.gardner@canonical.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_debugfs.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_debugfs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 0a893f7..e36efdc 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -865,7 +865,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) MEMSTAT_VID_SHIFT); seq_printf(m, "Current P-state: %d\n", (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); - } else if (IS_GEN6(dev)) { + } else if (IS_GEN6(dev) || IS_GEN7(dev)) { u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |