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| author | Alex Deucher <alexdeucher@gmail.com> | 2010-09-04 05:04:34 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-10-06 11:38:08 +1000 |
| commit | d0f8a854c340986359a3b0a97e380c71def7a440 (patch) | |
| tree | 4f4065bb8c920badc92f56c25b5b105066ae6fc2 /drivers/gpu/drm/radeon/radeon.h | |
| parent | 724c80e1d630296d1324859e964d80d35007d83c (diff) | |
| download | kernel_samsung_smdk4412-d0f8a854c340986359a3b0a97e380c71def7a440.zip kernel_samsung_smdk4412-d0f8a854c340986359a3b0a97e380c71def7a440.tar.gz kernel_samsung_smdk4412-d0f8a854c340986359a3b0a97e380c71def7a440.tar.bz2 | |
drm/radeon/kms/r6xx+: use new style fencing (v3)
On r6xx+ a newer fence mechanism was implemented to replace
the old wait_until plus scratch regs setup. A single EOP event
will flush the destination caches, write a fence value, and generate
an interrupt. This is the recommended fence mechanism on r6xx+ asics.
This requires my previous writeback patch.
v2: fix typo that enabled event fence checking on all asics
rather than just r6xx+.
v3: properly enable EOP interrupts
Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=29972
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 4e10938..2bfae56 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -595,11 +595,13 @@ struct radeon_wb { volatile uint32_t *wb; uint64_t gpu_addr; bool enabled; + bool use_event; }; #define RADEON_WB_SCRATCH_OFFSET 0 #define RADEON_WB_CP_RPTR_OFFSET 1024 #define R600_WB_IH_WPTR_OFFSET 2048 +#define R600_WB_EVENT_OFFSET 3072 /** * struct radeon_pm - power management datas |