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| author | Dave Airlie <airlied@redhat.com> | 2011-03-11 21:17:41 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2011-03-13 10:03:34 +1000 |
| commit | c640e8ca172c6a5c45abe8e2e8353900a84427fa (patch) | |
| tree | c40b26bf9cf90a5fdcb43d475d2d3559dcd7e131 /drivers/gpu/drm/radeon/radeon_legacy_crtc.c | |
| parent | fdc315a19a2c33da29dd87d4ca88f4e4407bd42d (diff) | |
| download | kernel_samsung_smdk4412-c640e8ca172c6a5c45abe8e2e8353900a84427fa.zip kernel_samsung_smdk4412-c640e8ca172c6a5c45abe8e2e8353900a84427fa.tar.gz kernel_samsung_smdk4412-c640e8ca172c6a5c45abe8e2e8353900a84427fa.tar.bz2 | |
drm/radeon: fix page flipping hangs on r300/r400
We've been getting reports of complete system lockups with rv3xx hw on
AGP and PCIE when running gnome-shell or kwin with compositing.
It appears the hw really doesn't like setting these registers while
stuff is running, this moves the setting of the registers into the modeset
since they aren't required to be changed anywhere else.
fixes: https://bugs.freedesktop.org/show_bug.cgi?id=35183
Reported-and-tested-by: Álmos <aaalmosss@gmail.com
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_legacy_crtc.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index cf0638c..78968b7 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c @@ -443,7 +443,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, (target_fb->bits_per_pixel * 8)); crtc_pitch |= crtc_pitch << 16; - + crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; if (tiling_flags & RADEON_TILING_MACRO) { if (ASIC_IS_R300(rdev)) crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | @@ -502,6 +502,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, gen_cntl_val = RREG32(gen_cntl_reg); gen_cntl_val &= ~(0xf << 8); gen_cntl_val |= (format << 8); + gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; WREG32(gen_cntl_reg, gen_cntl_val); crtc_offset = (u32)base; |