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author | codeworkx <codeworkx@cyanogenmod.com> | 2012-09-22 09:48:20 +0200 |
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committer | codeworkx <codeworkx@cyanogenmod.com> | 2012-09-22 14:02:16 +0200 |
commit | 2489007e7d740ccbc3e0a202914e243ad5178787 (patch) | |
tree | b8e6380ea7b1da63474ad68a5dba997e01146043 /drivers/media/tdmb/tcc3170/src/tcbd_hal.c | |
parent | 5f67568eb31e3a813c7c52461dcf66ade15fc2e7 (diff) | |
download | kernel_samsung_smdk4412-2489007e7d740ccbc3e0a202914e243ad5178787.zip kernel_samsung_smdk4412-2489007e7d740ccbc3e0a202914e243ad5178787.tar.gz kernel_samsung_smdk4412-2489007e7d740ccbc3e0a202914e243ad5178787.tar.bz2 |
merge opensource jb u5
Change-Id: I1aaec157aa196f3448eff8636134fce89a814cf2
Diffstat (limited to 'drivers/media/tdmb/tcc3170/src/tcbd_hal.c')
-rw-r--r-- | drivers/media/tdmb/tcc3170/src/tcbd_hal.c | 42 |
1 files changed, 35 insertions, 7 deletions
diff --git a/drivers/media/tdmb/tcc3170/src/tcbd_hal.c b/drivers/media/tdmb/tcc3170/src/tcbd_hal.c index 43c2eb3..fba77e7 100644 --- a/drivers/media/tdmb/tcc3170/src/tcbd_hal.c +++ b/drivers/media/tdmb/tcc3170/src/tcbd_hal.c @@ -30,7 +30,10 @@ #include "tcpal_os.h" #include "tcpal_debug.h" #include "tcbd_hal.h" +#include "tcbd_feature.h" +#define __USE_DXB0_IRQ__ +/*#define __USE_DXB1_IRQ__*/ #ifdef __USE_TC_CPU__ static PGPIO RGPIO; @@ -51,22 +54,38 @@ void tchal_reset_device(void) { #ifdef __USE_TC_CPU__ tcbd_debug(DEBUG_TCHAL, "\n"); - +#if defined(__CSPI_ONLY__) /* select peripheral mode as SPI */ +#if defined(__USE_DXB1_IRQ__) BITCLR(RGPIO->GPAFN1, Hw16 - Hw12); /* DXB1_IRQ Set GPIO mode*/ BITSET(RGPIO->GPAEN, Hw11); /* DXB1_IRQ output mode*/ BITCLR(RGPIO->GPADAT, Hw11); /* DXB1_IRQ clear*/ +#elif defined(__USE_DXB0_IRQ__) + BITCLR(RGPIO->GPDFN1, Hw8 - Hw4); /* DXB0_IRQ Set GPIO mode*/ + BITSET(RGPIO->GPDEN, Hw9); /* DXB0_IRQ output mode*/ + BITCLR(RGPIO->GPDDAT, Hw9); /* DXB0_IRQ clear*/ +#endif /*__USE_DXB1_IRQ__*/ +#endif /*__CSPI_ONLY__*/ /* reset */ +#if defined(__CSPI_ONLY__) BITCLR(RGPIO->GPEFN1, Hw16 - Hw12); /* DXB1_RST# Set GPIO mode */ BITSET(RGPIO->GPEEN, Hw11);/* DXB1_RST# Set GPIO Output mode*/ BITCLR(RGPIO->GPEDAT, Hw11);/* DXB1_RST# Clear */ tcpal_msleep(10); BITSET(RGPIO->GPEDAT, Hw11);/* DXB1_RST# Set*/ +#elif defined(__I2C_STS__) + BITCLR(RGPIO->GPDFN1, Hw4 - Hw0); /* DXB0_RST# Set GPIO mode */ + BITSET(RGPIO->GPDEN, Hw8); /* DXB0_RST# Set GPIO Output mode*/ + BITCLR(RGPIO->GPDDAT, Hw8); /* DXB0_RST# Clear */ + tcpal_msleep(10); + BITSET(RGPIO->GPDDAT, Hw8); /* DXB0_RST# Set*/ +#else /*__CSPI_ONLY__ || __I2C_STS__*/ +#error "you must define __CSPI_ONLY__ or __I2C_STS__" +#endif /*!__CSPI_ONLY__ && !__I2C_STS__*/ #endif } - void tchal_power_on_device(void) { #ifdef __USE_TC_CPU__ @@ -92,21 +111,30 @@ void tchal_power_down_device(void) BITCLR(RGPIO->GPEFN0, Hw16 - Hw12); BITSET(RGPIO->GPEEN, Hw3);/* DXB1_PD Set GPIO Output mode*/ BITCLR(RGPIO->GPEDAT, Hw3);/* DXB1_PD Clear*/ +#if defined(__CSPI_ONLY__) BITCLR(RGPIO->GPEDAT, Hw11);/* DXB1_RST# Clear*/ - - BITCLR(RGPIO->GPAFN1, Hw16 - Hw12);/* DXB1_RST# Set GPIO mode*/ - BITSET(RGPIO->GPAEN, Hw11);/* DXB1_RST# Set GPIO Output mode*/ - BITCLR(RGPIO->GPADAT, Hw11);/* DXB1_RST# Clear*/ +#elif defined(__I2C_STS__) + BITCLR(RGPIO->GPDDAT, Hw8);/* DXB0_RST# Clear */ +#else +#error "you must define __CSPI_ONLY__ or __I2C_STS__" +#endif #endif } void tchal_irq_setup(void) { #ifdef __USE_TC_CPU__ +#if defined(__USE_DXB1_IRQ__) BITCLR(RGPIO->GPAFN1, Hw16 - Hw12);/* DXB1_IRQ Set GPIO mode*/ BITCLR(RGPIO->GPAEN, Hw11);/* DXB1_IRQ input mode*/ - BITCSET(RGPIO->EINTSEL0, Hw32 - Hw24, 11<<24); + BITCSET(RGPIO->EINTSEL0, Hw32 - Hw24, 11<<24); /*GPIO_A11*/ +#elif defined(__USE_DXB0_IRQ__) + BITCLR(RGPIO->GPDFN1, Hw8 - Hw4); /* DXB0_IRQ Set GPIO mode*/ + BITCLR(RGPIO->GPDEN, Hw9); /* DXB0_IRQ input mode*/ + + BITCSET(RGPIO->EINTSEL0, Hw32 - Hw24, 20<<24); /*GPIO_D9*/ +#endif /*__USE_DXB1_IRQ__*/ BITSET(RPIC->POL0, 1<<IRQ_TC317X); #endif } |