smdk4412: mali: merge with r3p1 driver from note8

Change-Id: I75db69081b986ec326fe347f73aa3655648e6b81

3 files changed, 67 insertions, 71 deletions

diff --git a/drivers/media/video/samsung/mali/platform/orion-m400/mali_platform.c b/drivers/media/video/samsung/mali/platform/orion-m400/mali_platform.c
index 792b9a9..119831d 100644
--- a/drivers/media/video/samsung/mali/platform/orion-m400/mali_platform.c
+++ b/drivers/media/video/samsung/mali/platform/orion-m400/mali_platform.c
@@ -1,9 +1,9 @@
 /*
  * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
- * 
+ *
  * This program is free software and is provided to you under the terms of the GNU General Public License version 2
  * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
- * 
+ *
  * A copy of the licence is included with the program, and can also be obtained from Free Software
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
@@ -19,7 +19,7 @@
 #include "mali_linux_pm.h"
 
 #if USING_MALI_PMM
-#include "mali_pmm.h"
+#include "mali_pm.h"
 #endif
 
 #include <linux/clk.h>
@@ -156,7 +156,7 @@ void mali_regulator_set_voltage(int min_uV, int max_uV)
 		return;
 	}
 	MALI_DEBUG_PRINT(2, ("= regulator_set_voltage: %d, %d \n",min_uV, max_uV));
-	
+
 #if MALI_TIMELINE_PROFILING_ENABLED
     _mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
                                MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
@@ -166,7 +166,7 @@ void mali_regulator_set_voltage(int min_uV, int max_uV)
 
 	regulator_set_voltage(g3d_regulator,min_uV,max_uV);
 	voltage = regulator_get_voltage(g3d_regulator);
-	
+
 #if MALI_TIMELINE_PROFILING_ENABLED
     _mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
                                MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
@@ -178,7 +178,7 @@ void mali_regulator_set_voltage(int min_uV, int max_uV)
 
 	_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
 }
-#endif  
+#endif
 
 unsigned long mali_clk_get_rate(void)
 {
@@ -228,7 +228,7 @@ mali_bool mali_clk_get(mali_bool bis_vpll)
 		if (mali_parent_clock == NULL)
 		{
 			mali_parent_clock = clk_get(NULL, GPUMOUT1CLK_NAME);
-		
+
 			if (IS_ERR(mali_parent_clock)) {
 				MALI_PRINT( ( "MALI Error : failed to get source mali parent clock\n"));
 				return MALI_FALSE;
@@ -279,7 +279,7 @@ void mali_clk_put(mali_bool binc_mali_clock)
 		clk_put(mali_parent_clock);
 		mali_parent_clock = 0;
 	}
-	
+
 	if (mpll_clock)
 	{
 		clk_put(mpll_clock);
@@ -303,7 +303,7 @@ void mali_clk_put(mali_bool binc_mali_clock)
 		clk_put(vpll_src_clock);
 		vpll_src_clock = 0;
 	}
-	
+
 	if (ext_xtal_clock)
 	{
 		clk_put(ext_xtal_clock);
@@ -382,14 +382,14 @@ mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz)
 	mali_clk_put(MALI_FALSE);
 
 	_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
-	
+
 	return MALI_TRUE;
 }
 
 static mali_bool init_mali_clock(void)
 {
 	mali_bool ret = MALI_TRUE;
-	
+
 	gpu_power_state = 0;
 
 	if (mali_clock != 0)
@@ -416,7 +416,7 @@ static mali_bool init_mali_clock(void)
 	g3d_regulator = regulator_get(NULL, "vdd_g3d");
 #endif
 
-	if (IS_ERR(g3d_regulator)) 
+	if (IS_ERR(g3d_regulator))
 	{
 		MALI_PRINT( ("MALI Error : failed to get vdd_g3d\n"));
 		ret = MALI_FALSE;
@@ -429,8 +429,6 @@ static mali_bool init_mali_clock(void)
 #endif
 
 	MALI_DEBUG_PRINT(2, ("MALI Clock is set at mali driver\n"));
-	
-
 	MALI_DEBUG_PRINT(3,("::clk_put:: %s mali_parent_clock - normal\n", __FUNCTION__));
 	MALI_DEBUG_PRINT(3,("::clk_put:: %s mpll_clock  - normal\n", __FUNCTION__));
 
@@ -443,7 +441,7 @@ static mali_bool init_mali_clock(void)
 err_regulator:
 	regulator_put(g3d_regulator);
 #endif
-	
+
 err_clock_get:
 	mali_clk_put(MALI_TRUE);
 
@@ -456,7 +454,7 @@ static mali_bool deinit_mali_clock(void)
 		return MALI_TRUE;
 
 #ifdef CONFIG_REGULATOR
-	if (g3d_regulator) 
+	if (g3d_regulator)
 	{
 		regulator_put(g3d_regulator);
 		g3d_regulator=NULL;
@@ -506,8 +504,8 @@ _mali_osk_errcode_t g3d_power_domain_control(int bpower_on)
 	if (bpower_on)
 	{
 #if MALI_PMM_RUNTIME_JOB_CONTROL_ON
-		MALI_DEBUG_PRINT(3,("_mali_osk_pmm_dev_activate \n"));
-		_mali_osk_pmm_dev_activate();
+		MALI_DEBUG_PRINT(3,("_mali_osk_pm_dev_activate \n"));
+		_mali_osk_pm_dev_activate();
 #else //MALI_PMM_RUNTIME_JOB_CONTROL_ON
 		void __iomem *status;
 		u32 timeout;
@@ -529,14 +527,14 @@ _mali_osk_errcode_t g3d_power_domain_control(int bpower_on)
 	else
 	{
 #if MALI_PMM_RUNTIME_JOB_CONTROL_ON
-		MALI_DEBUG_PRINT( 4,("_mali_osk_pmm_dev_idle\n"));
-		_mali_osk_pmm_dev_idle();
+		MALI_DEBUG_PRINT( 4,("_mali_osk_pm_dev_idle\n"));
+		_mali_osk_pm_dev_idle();
 
 #else //MALI_PMM_RUNTIME_JOB_CONTROL_ON
 		void __iomem *status;
 		u32 timeout;
 		__raw_writel(0, S5P_PMU_G3D_CONF);
-		
+
 		status = S5P_PMU_G3D_CONF + 0x4;
 		/* Wait max 1ms */
 		timeout = 10;
@@ -561,7 +559,7 @@ _mali_osk_errcode_t mali_platform_init()
 #if MALI_DVFS_ENABLED
 	if (!clk_register_map) clk_register_map = _mali_osk_mem_mapioregion( CLK_DIV_STAT_G3D, 0x20, CLK_DESC );
 	if(!init_mali_dvfs_status(MALI_DVFS_DEFAULT_STEP))
-		MALI_DEBUG_PRINT(1, ("mali_platform_init failed\n"));        
+		MALI_DEBUG_PRINT(1, ("mali_platform_init failed\n"));
 #endif
 
     MALI_SUCCESS;
@@ -593,7 +591,7 @@ _mali_osk_errcode_t mali_platform_powerdown(u32 cores)
 		if (gpu_power_state == 0)
 		{
 			MALI_DEBUG_PRINT( 3,("disable clock\n"));
-			disable_mali_clocks();			
+			disable_mali_clocks();
 		}
 	}
 	else
@@ -635,7 +633,7 @@ _mali_osk_errcode_t mali_platform_powerup(u32 cores)
 
 void mali_gpu_utilization_handler(u32 utilization)
 {
-	if (bPoweroff==0) 
+	if (bPoweroff==0)
 	{
 #if MALI_DVFS_ENABLED
 		if(!mali_dvfs_handler(utilization))
diff --git a/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform.c b/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform.c
index 8fc26cd..a08bc97 100644
--- a/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform.c
+++ b/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform.c
@@ -33,7 +33,8 @@
 
 #if MALI_INTERNAL_TIMELINE_PROFILING_ENABLED
 #include "mali_osk_profiling.h"
-#include "cinstr/mali_cinstr_profiling_events_m200.h"
+unsigned long gFreq = 366;
+int gVolt = 5000;
 #endif
 
 #include <asm/io.h>
@@ -58,7 +59,7 @@ typedef struct mali_runtime_resumeTag{
 	int vol;
 }mali_runtime_resume_table;
 
-mali_runtime_resume_table mali_runtime_resume = {350, 950000};
+mali_runtime_resume_table mali_runtime_resume = {266, 900000};
 
 /* lock/unlock CPU freq by Mali */
 extern int cpufreq_lock_by_mali(unsigned int freq);
@@ -84,11 +85,11 @@ static struct clk  *mali_clock = 0;
 
 static unsigned int GPU_MHZ	= 1000000;
 
-int mali_gpu_clk = 350;
-int mali_gpu_vol = 950000;
+int mali_gpu_clk = 266;
+int mali_gpu_vol = 900000;
 
 #if MALI_DVFS_ENABLED
-#define MALI_DVFS_DEFAULT_STEP 2
+#define MALI_DVFS_DEFAULT_STEP 1
 #endif
 #if MALI_VOLTAGE_LOCK
 int mali_lock_vol = 0;
@@ -204,21 +205,15 @@ void mali_regulator_set_voltage(int min_uV, int max_uV)
 
     MALI_DEBUG_PRINT(2, ("= regulator_set_voltage: %d, %d \n",min_uV, max_uV));
 
-#if MALI_INTERNAL_TIMELINE_PROFILING_ENABLED
-    _mali_osk_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
-                               MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
-                               MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_VOLTS,
-                               min_uV, max_uV, 1, 0, 0);
-#endif
-
     regulator_set_voltage(g3d_regulator,min_uV,max_uV);
 	voltage = regulator_get_voltage(g3d_regulator);
 
 #if MALI_INTERNAL_TIMELINE_PROFILING_ENABLED
-    _mali_osk_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
-                               MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
-                               MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_VOLTS,
-                               voltage, 0, 2, 0, 0);
+	gVolt = voltage/1000;
+	_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | 
+				MALI_PROFILING_EVENT_CHANNEL_GPU | 
+				MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, gFreq, gVolt, 
+				0, 0, 0); 
 #endif
 
 	mali_gpu_vol = voltage;
@@ -379,7 +374,7 @@ mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz)
 #if !MALI_DVFS_ENABLED
 	clk = mali_gpu_clk;
 #endif
-
+	trace_printk("SPI_GPUFREQ_%uMHz\n", mali_gpu_clk);
 	_mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
 
 	if (mali_clk_get(bis_vpll) == MALI_FALSE)
@@ -406,23 +401,16 @@ mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz)
 	if (clk_enable(mali_clock) < 0)
 		return MALI_FALSE;
 
-#if MALI_INTERNAL_TIMELINE_PROFILING_ENABLED
-    unsigned long previous_rate = 0;
-    previous_rate = clk_get_rate(mali_clock);
-    _mali_osk_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
-                               MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
-                               MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ,
-                               previous_rate, 0, 0, 0, 0);
-#endif
 
 	clk_set_rate(mali_clock, rate);
 	rate = clk_get_rate(mali_clock);
 
 #if MALI_INTERNAL_TIMELINE_PROFILING_ENABLED
-    _mali_osk_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
-                               MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
-                               MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ,
-                               rate, 1, 0, 0, 0);
+	gFreq = rate/1000000;
+	_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | 
+				MALI_PROFILING_EVENT_CHANNEL_GPU | 
+				MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, 
+				gFreq, gVolt, 0, 0, 0); 
 #endif
 
 	if (bis_vpll)
@@ -539,7 +527,7 @@ static _mali_osk_errcode_t enable_mali_clocks(void)
 	}
 #if CPUFREQ_LOCK_DURING_440
 	/* lock/unlock CPU freq by Mali */
-	if (mali_gpu_clk == 440)
+	if (mali_gpu_clk >= 440)
 		err = cpufreq_lock_by_mali(1200);
 #endif
 #else
@@ -557,7 +545,7 @@ static _mali_osk_errcode_t disable_mali_clocks(void)
 	clk_disable(mali_clock);
 	MALI_DEBUG_PRINT(3,("disable_mali_clocks mali_clock %p \n", mali_clock));
 
-#if MALI_DVFS_ENABLED
+#if MALI_DVFS_ENABLED && CPUFREQ_LOCK_DURING_440
 	/* lock/unlock CPU freq by Mali */
 	cpufreq_unlock_by_mali();
 #endif
@@ -598,7 +586,6 @@ _mali_osk_errcode_t g3d_power_domain_control(int bpower_on)
 			timeout--;
 			_mali_osk_time_ubusydelay(100);
 		}
-		MALI_PRINTF(("MALI Power domain enabled"));		
 #endif //MALI_PMM_RUNTIME_JOB_CONTROL_ON
 	}
 	else
@@ -623,7 +610,6 @@ _mali_osk_errcode_t g3d_power_domain_control(int bpower_on)
 			timeout--;
 			_mali_osk_time_ubusydelay( 100);
 		}
-		MALI_PRINTF(("MALI Power domain disabled"));
 #endif //MALI_PMM_RUNTIME_JOB_CONTROL_ON
 	}
 
@@ -665,6 +651,7 @@ _mali_osk_errcode_t mali_platform_deinit()
 
 _mali_osk_errcode_t mali_platform_powerdown(u32 cores)
 {
+	trace_printk("SPI_GPU_PWR Idle\n");
 	MALI_DEBUG_PRINT(3,("power down is called in mali_platform_powerdown state %x core %x \n", gpu_power_state, cores));
 
 	if (gpu_power_state != 0) // power down after state is 0
@@ -686,6 +673,7 @@ _mali_osk_errcode_t mali_platform_powerdown(u32 cores)
 
 _mali_osk_errcode_t mali_platform_powerup(u32 cores)
 {
+	trace_printk("SPI_GPU_PWR Start\n");
 	MALI_DEBUG_PRINT(3,("power up is called in mali_platform_powerup state %x core %x \n", gpu_power_state, cores));
 
 	if (gpu_power_state == 0) // power up only before state is 0
diff --git a/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform_dvfs.c b/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform_dvfs.c
index e83addd..cc1164e 100644
--- a/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform_dvfs.c
+++ b/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform_dvfs.c
@@ -175,6 +175,7 @@ mali_dvfs_threshold_table mali_dvfs_threshold[MALI_DVFS_STEPS]={
 
 #ifdef EXYNOS4_ASV_ENABLED
 #define ASV_LEVEL     12	/* ASV0, 1, 11 is reserved */
+#define ASV_LEVEL_PRIME     13	/* ASV0, 1, 12 is reserved */
 
 static unsigned int asv_3d_volt_9_table_1ghz_type[MALI_DVFS_STEPS-1][ASV_LEVEL] = {
 	{  975000,  950000,  950000,  950000,  925000,  925000,  925000,  900000,  900000,  900000,  900000,  875000},  /* L3(160Mhz) */
@@ -202,7 +203,7 @@ static unsigned int asv_3d_volt_9_table[MALI_DVFS_STEPS-1][ASV_LEVEL] = {
 #endif
 };
 
-static unsigned int asv_3d_volt_9_table_for_prime[MALI_DVFS_STEPS][ASV_LEVEL] = {
+static unsigned int asv_3d_volt_9_table_for_prime[MALI_DVFS_STEPS][ASV_LEVEL_PRIME] = {
 	{  950000,  937500,  925000,  912500,  900000,  887500,  875000,  862500,  875000,  862500,  850000,  850000},  /* L4(160Mhz) */
 #if (MALI_DVFS_STEPS > 1)
 	{  975000,  962500,  950000,  937500,  925000,  912500,  900000,  887500,  900000,  887500,  875000,  862500},	/* L3(266Mhz) */
@@ -211,7 +212,7 @@ static unsigned int asv_3d_volt_9_table_for_prime[MALI_DVFS_STEPS][ASV_LEVEL] =
 #if (MALI_DVFS_STEPS > 3)
 	{ 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 1012500, 1000000,  987500,  975000},	/* L1(440Mhz) */
 #if (MALI_DVFS_STEPS > 4)
-	{ 1150000, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1087500, 1075000, 1062500, 1050000},	/* L0(533Mhz) */
+	{ 1150000, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1087500, 1075000, 1062500, 1050000},	/* L0(600Mhz) */
 #endif
 #endif
 #endif
@@ -330,10 +331,12 @@ static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup)
 	}
 
 #ifdef EXYNOS4_ASV_ENABLED
-	if (mali_dvfs[step].clock == 160)
-		exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V);
-	else
-		exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V);
+	if (samsung_rev() < EXYNOS4412_REV_2_0) {
+		if (mali_dvfs[step].clock == 160)
+			exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V);
+		else
+			exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V);
+	}
 #endif
 
 
@@ -390,26 +393,33 @@ static mali_bool mali_dvfs_table_update(void)
 	unsigned int i;
 	unsigned int step_num = MALI_DVFS_STEPS;
 
+	if(samsung_rev() < EXYNOS4412_REV_2_0)
+		step_num = MALI_DVFS_STEPS - 1;
+
 	if(soc_is_exynos4412()) {
 		if (exynos_armclk_max == 1000000) {
-			step_num = MALI_DVFS_STEPS - 1;
+			MALI_PRINT(("::C::exynos_result_of_asv : %d\n", exynos_result_of_asv));
 			for (i = 0; i < step_num; i++) {
-				MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
 				mali_dvfs[i].vol = asv_3d_volt_9_table_1ghz_type[i][exynos_result_of_asv];
-				MALI_PRINT(("mali_dvfs[%d].vol = %d 1ghz_type\n", i, mali_dvfs[i].vol));
+				MALI_PRINT(("mali_dvfs[%d].vol = %d \n", i, mali_dvfs[i].vol));
+			}
+		} else if(((is_special_flag() >> G3D_LOCK_FLAG) & 0x1) && (samsung_rev() >= EXYNOS4412_REV_2_0)) {
+			MALI_PRINT(("::L::exynos_result_of_asv : %d\n", exynos_result_of_asv));
+			for (i = 0; i < step_num; i++) {
+				mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv] + 25000;
+				MALI_PRINT(("mali_dvfs[%d].vol = %d \n ", i, mali_dvfs[i].vol));
 			}
 		} else if (samsung_rev() >= EXYNOS4412_REV_2_0) {
+			MALI_PRINT(("::P::exynos_result_of_asv : %d\n", exynos_result_of_asv));
 			for (i = 0; i < step_num; i++) {
-				MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
 				mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv];
-				MALI_PRINT(("mali_dvfs[%d].vol = %d 1.6ghz_type\n", i, mali_dvfs[i].vol));
+				MALI_PRINT(("mali_dvfs[%d].vol = %d \n", i, mali_dvfs[i].vol));
 			}
 		} else {
-			step_num = MALI_DVFS_STEPS - 1;
+			MALI_PRINT(("::Q::exynos_result_of_asv : %d\n", exynos_result_of_asv));
 			for (i = 0; i < step_num; i++) {
-				MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
 				mali_dvfs[i].vol = asv_3d_volt_9_table[i][exynos_result_of_asv];
-				MALI_PRINT(("mali_dvfs[%d].vol = %d 1.4ghz_type\n", i, mali_dvfs[i].vol));
+				MALI_PRINT(("mali_dvfs[%d].vol = %d \n", i, mali_dvfs[i].vol));
 			}
 		}
 	}