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| author | Sujith <Sujith.Manoharan@atheros.com> | 2010-04-16 11:53:57 +0530 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2010-04-16 15:47:09 -0400 |
| commit | 7d0d0df0eca695c83a08dc386824a9d1d7c526a4 (patch) | |
| tree | df2104a15ef84bcd15478e956b3458241b3b7a78 /drivers/net/wireless/ath/ath9k/eeprom_4k.c | |
| parent | 6819d57f07440a8f9540967d9212a70e9c98eceb (diff) | |
| download | kernel_samsung_smdk4412-7d0d0df0eca695c83a08dc386824a9d1d7c526a4.zip kernel_samsung_smdk4412-7d0d0df0eca695c83a08dc386824a9d1d7c526a4.tar.gz kernel_samsung_smdk4412-7d0d0df0eca695c83a08dc386824a9d1d7c526a4.tar.bz2 | |
ath9k_hw: Use buffered register writes
This patch adds macros at certain places
which could be optimized for multiple register writes.
The performance of ath9k_htc improves considerably,
especially reducing the latency involved in a scan run.
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/eeprom_4k.c')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/eeprom_4k.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c index 2384a9f..41a77d1 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c +++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c @@ -454,6 +454,8 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, &tMinCalPower, gainBoundaries, pdadcValues, numXpdGain); + ENABLE_REGWRITE_BUFFER(ah); + if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) { REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, SM(pdGainOverlap_t2, @@ -494,6 +496,9 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, regOffset += 4; } + + REGWRITE_BUFFER_FLUSH(ah); + DISABLE_REGWRITE_BUFFER(ah); } } @@ -759,6 +764,8 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah, ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; } + ENABLE_REGWRITE_BUFFER(ah); + /* OFDM power per rate */ REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, ATH9K_POW_SM(ratesArray[rate18mb], 24) @@ -821,6 +828,9 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah, | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); } + + REGWRITE_BUFFER_FLUSH(ah); + DISABLE_REGWRITE_BUFFER(ah); } static void ath9k_hw_4k_set_addac(struct ath_hw *ah, |