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| author | codeworkx <daniel.hillenbrand@codeworkx.de> | 2012-06-02 13:09:29 +0200 |
|---|---|---|
| committer | codeworkx <daniel.hillenbrand@codeworkx.de> | 2012-06-02 13:09:29 +0200 |
| commit | c6da2cfeb05178a11c6d062a06f8078150ee492f (patch) | |
| tree | f3b4021d252c52d6463a9b3c1bb7245e399b009c /include/asm-generic | |
| parent | c6d7c4dbff353eac7919342ae6b3299a378160a6 (diff) | |
| download | kernel_samsung_smdk4412-c6da2cfeb05178a11c6d062a06f8078150ee492f.zip kernel_samsung_smdk4412-c6da2cfeb05178a11c6d062a06f8078150ee492f.tar.gz kernel_samsung_smdk4412-c6da2cfeb05178a11c6d062a06f8078150ee492f.tar.bz2 | |
samsung update 1
Diffstat (limited to 'include/asm-generic')
| -rw-r--r-- | include/asm-generic/smc.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/include/asm-generic/smc.h b/include/asm-generic/smc.h new file mode 100644 index 0000000..cf5ec0a --- /dev/null +++ b/include/asm-generic/smc.h @@ -0,0 +1,53 @@ +/* linux/arch/arm/mach-exynos/include/mach/smc.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS - SMC Call + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_SMC_H +#define __ASM_ARCH_SMC_H __FILE__ + +#define SMC_CMD_INIT (-1) +#define SMC_CMD_INFO (-2) +/* For Power Management */ +#define SMC_CMD_SLEEP (-3) +#define SMC_CMD_CPU1BOOT (-4) +#define SMC_CMD_CPU0AFTR (-5) +/* For CP15 Access */ +#define SMC_CMD_C15RESUME (-11) +/* For L2 Cache Access */ +#define SMC_CMD_L2X0CTRL (-21) +#define SMC_CMD_L2X0SETUP1 (-22) +#define SMC_CMD_L2X0SETUP2 (-23) +#define SMC_CMD_L2X0INVALL (-24) +#define SMC_CMD_L2X0DEBUG (-25) + +/* For Accessing CP15/SFR (General) */ +#define SMC_CMD_REG (-101) + +/* For Custom Binary Info. Access */ +#define SMC_CMD_STORE_BINFO (-201) + +/* MACRO for SMC_CMD_REG */ +#define SMC_REG_CLASS_CP15 (0x0 << 30) +#define SMC_REG_CLASS_SFR_W (0x1 << 30) +#define SMC_REG_CLASS_SFR_R (0x3 << 30) +#define SMC_REG_CLASS_MASK (0x3 << 30) +#define SMC_REG_ID_CP15(CRn, Op1, CRm, Op2) \ + (SMC_REG_CLASS_CP15 | \ + ((CRn) << 10) | ((Op1) << 7) | ((CRm) << 3) | (Op2)) +#define SMC_REG_ID_SFR_W(ADDR) (SMC_REG_CLASS_SFR_W | ((ADDR) >> 2)) +#define SMC_REG_ID_SFR_R(ADDR) (SMC_REG_CLASS_SFR_R | ((ADDR) >> 2)) + +#ifndef __ASSEMBLY__ +extern u32 exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3); +extern u32 exynos_smc_readsfr(u32 addr, u32 *val); +#endif + +#endif /* __ASM_ARCH_SMC_H */ |