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authorSonic Zhang <sonic.zhang@analog.com>2008-04-24 06:13:37 +0800
committerBryan Wu <cooloney@kernel.org>2008-04-24 06:13:37 +0800
commitb85b82d980526d683dc3b39f2ac1f447fa84a105 (patch)
tree116646f10fc37668b4136aa040136354442eeb54 /include/asm-xtensa
parent253bcf4f9b6dde1cfa169bc29655cf177d6a903b (diff)
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[Blackfin] arch: fix bug - Section data_l1_cacheline_aligned should be defined in link script of kernel
http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3978 Section data_l1_cacheline_aligned should be defined in link script of kernel, when L1 data sram bank A is not available. In bf536 with all data cache is enabled, there is no L1 data sram. Current link script won't define section data_l1.cacheline_aligned in this case. But, if user select put cacheline_aligned data into l1 sram in kernel menuconfig, these data will be dropped and access to these data will trigger data CPLB exception. Do panic in l1 relocation code as well. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-xtensa')
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