samsung update 1

15 files changed, 2550 insertions, 366 deletions

diff --git a/include/linux/mfd/max77686-private.h b/include/linux/mfd/max77686-private.h
new file mode 100644
index 0000000..17273d5
--- /dev/null
+++ b/include/linux/mfd/max77686-private.h
@@ -0,0 +1,259 @@
+/*
+ * max77686.h - Voltage regulator driver for the Maxim 77686
+ *
+ *  Copyright (C) 2011 Samsung Electrnoics
+ *  Chiwoong Byun <woong.byun@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_MFD_MAX77686_PRIV_H
+#define __LINUX_MFD_MAX77686_PRIV_H
+
+#include <linux/i2c.h>
+
+#define MAX77686_REG_INVALID		(0xff)
+
+enum max77686_pmic_reg {
+	MAX77686_REG_DEVICE_ID		= 0x00,
+	MAX77686_REG_INTSRC		= 0x01,
+	MAX77686_REG_INT1		= 0x02,
+	MAX77686_REG_INT2		= 0x03,
+
+	MAX77686_REG_INT1MSK		= 0x04,
+	MAX77686_REG_INT2MSK		= 0x05,
+
+	MAX77686_REG_STATUS1		= 0x06,
+	MAX77686_REG_STATUS2		= 0x07,
+
+	MAX77686_REG_PWRON		= 0x08,
+	MAX77686_REG_ONOFF_DELAY	= 0x09,
+	MAX77686_REG_MRSTB		= 0x0A,
+	/* Reserved: 0x0B-0x0F */
+
+	MAX77686_REG_BUCK1CTRL		= 0x10,
+	MAX77686_REG_BUCK1OUT		= 0x11,
+	MAX77686_REG_BUCK2CTRL1		= 0x12,
+	MAX77686_REG_BUCK234FREQ	= 0x13,
+	MAX77686_REG_BUCK2DVS1		= 0x14,
+	MAX77686_REG_BUCK2DVS2		= 0x15,
+	MAX77686_REG_BUCK2DVS3		= 0x16,
+	MAX77686_REG_BUCK2DVS4		= 0x17,
+	MAX77686_REG_BUCK2DVS5		= 0x18,
+	MAX77686_REG_BUCK2DVS6		= 0x19,
+	MAX77686_REG_BUCK2DVS7		= 0x1A,
+	MAX77686_REG_BUCK2DVS8		= 0x1B,
+	MAX77686_REG_BUCK3CTRL1		= 0x1C,
+	/* Reserved: 0x1D */
+	MAX77686_REG_BUCK3DVS1		= 0x1E,
+	MAX77686_REG_BUCK3DVS2		= 0x1F,
+	MAX77686_REG_BUCK3DVS3		= 0x20,
+	MAX77686_REG_BUCK3DVS4		= 0x21,
+	MAX77686_REG_BUCK3DVS5		= 0x22,
+	MAX77686_REG_BUCK3DVS6		= 0x23,
+	MAX77686_REG_BUCK3DVS7		= 0x24,
+	MAX77686_REG_BUCK3DVS8		= 0x25,
+	MAX77686_REG_BUCK4CTRL1		= 0x26,
+	/* Reserved: 0x27 */
+	MAX77686_REG_BUCK4DVS1		= 0x28,
+	MAX77686_REG_BUCK4DVS2		= 0x29,
+	MAX77686_REG_BUCK4DVS3		= 0x2A,
+	MAX77686_REG_BUCK4DVS4		= 0x2B,
+	MAX77686_REG_BUCK4DVS5		= 0x2C,
+	MAX77686_REG_BUCK4DVS6		= 0x2D,
+	MAX77686_REG_BUCK4DVS7		= 0x2E,
+	MAX77686_REG_BUCK4DVS8		= 0x2F,
+	MAX77686_REG_BUCK5CTRL		= 0x30,
+	MAX77686_REG_BUCK5OUT		= 0x31,
+	MAX77686_REG_BUCK6CTRL		= 0x32,
+	MAX77686_REG_BUCK6OUT		= 0x33,
+	MAX77686_REG_BUCK7CTRL		= 0x34,
+	MAX77686_REG_BUCK7OUT		= 0x35,
+	MAX77686_REG_BUCK8CTRL		= 0x36,
+	MAX77686_REG_BUCK8OUT		= 0x37,
+	MAX77686_REG_BUCK9CTRL		= 0x38,
+	MAX77686_REG_BUCK9OUT		= 0x39,
+	/* Reserved: 0x3A-0x3F */
+
+	MAX77686_REG_LDO1CTRL1		= 0x40,
+	MAX77686_REG_LDO2CTRL1		= 0x41,
+	MAX77686_REG_LDO3CTRL1		= 0x42,
+	MAX77686_REG_LDO4CTRL1		= 0x43,
+	MAX77686_REG_LDO5CTRL1		= 0x44,
+	MAX77686_REG_LDO6CTRL1		= 0x45,
+	MAX77686_REG_LDO7CTRL1		= 0x46,
+	MAX77686_REG_LDO8CTRL1		= 0x47,
+	MAX77686_REG_LDO9CTRL1		= 0x48,
+	MAX77686_REG_LDO10CTRL1		= 0x49,
+	MAX77686_REG_LDO11CTRL1		= 0x4A,
+	MAX77686_REG_LDO12CTRL1		= 0x4B,
+	MAX77686_REG_LDO13CTRL1		= 0x4C,
+	MAX77686_REG_LDO14CTRL1		= 0x4D,
+	MAX77686_REG_LDO15CTRL1		= 0x4E,
+	MAX77686_REG_LDO16CTRL1		= 0x4F,
+	MAX77686_REG_LDO17CTRL1		= 0x50,
+	MAX77686_REG_LDO18CTRL1		= 0x51,
+	MAX77686_REG_LDO19CTRL1		= 0x52,
+	MAX77686_REG_LDO20CTRL1		= 0x53,
+	MAX77686_REG_LDO21CTRL1		= 0x54,
+	MAX77686_REG_LDO22CTRL1		= 0x55,
+	MAX77686_REG_LDO23CTRL1		= 0x56,
+	MAX77686_REG_LDO24CTRL1		= 0x57,
+	MAX77686_REG_LDO25CTRL1		= 0x58,
+	MAX77686_REG_LDO26CTRL1		= 0x59,
+	/* Reserved: 0x5A-0x5F */
+	MAX77686_REG_LDO1CTRL2		= 0x60,
+	MAX77686_REG_LDO2CTRL2		= 0x61,
+	MAX77686_REG_LDO3CTRL2		= 0x62,
+	MAX77686_REG_LDO4CTRL2		= 0x63,
+	MAX77686_REG_LDO5CTRL2		= 0x64,
+	MAX77686_REG_LDO6CTRL2		= 0x65,
+	MAX77686_REG_LDO7CTRL2		= 0x66,
+	MAX77686_REG_LDO8CTRL2		= 0x67,
+	MAX77686_REG_LDO9CTRL2		= 0x68,
+	MAX77686_REG_LDO10CTRL2		= 0x69,
+	MAX77686_REG_LDO11CTRL2		= 0x6A,
+	MAX77686_REG_LDO12CTRL2		= 0x6B,
+	MAX77686_REG_LDO13CTRL2		= 0x6C,
+	MAX77686_REG_LDO14CTRL2		= 0x6D,
+	MAX77686_REG_LDO15CTRL2		= 0x6E,
+	MAX77686_REG_LDO16CTRL2		= 0x6F,
+	MAX77686_REG_LDO17CTRL2		= 0x70,
+	MAX77686_REG_LDO18CTRL2		= 0x71,
+	MAX77686_REG_LDO19CTRL2		= 0x72,
+	MAX77686_REG_LDO20CTRL2		= 0x73,
+	MAX77686_REG_LDO21CTRL2		= 0x74,
+	MAX77686_REG_LDO22CTRL2		= 0x75,
+	MAX77686_REG_LDO23CTRL2		= 0x76,
+	MAX77686_REG_LDO24CTRL2		= 0x77,
+	MAX77686_REG_LDO25CTRL2		= 0x78,
+	MAX77686_REG_LDO26CTRL2		= 0x79,
+	/* Reserved: 0x7A-0x7D */
+
+	MAX77686_REG_BBAT_CHG		= 0x7E,
+	MAX77686_REG_32KHZ			= 0x7F,
+
+	MAX77686_REG_PMIC_END		= 0x80,
+};
+
+enum max77686_rtc_reg {
+	MAX77686_RTC_INT			= 0x00,
+	MAX77686_RTC_INTM			= 0x01,
+	MAX77686_RTC_CONTROLM		= 0x02,
+	MAX77686_RTC_CONTROL		= 0x03,
+	MAX77686_RTC_UPDATE0		= 0x04,
+	/* Reserved: 0x5 */
+	MAX77686_WTSR_SMPL_CNTL		= 0x06,
+	MAX77686_RTC_SEC			= 0x07,
+	MAX77686_RTC_MIN			= 0x08,
+	MAX77686_RTC_HOUR			= 0x09,
+	MAX77686_RTC_WEEKDAY		= 0x0A,
+	MAX77686_RTC_MONTH			= 0x0B,
+	MAX77686_RTC_YEAR			= 0x0C,
+	MAX77686_RTC_DATE			= 0x0D,
+	MAX77686_ALARM1_SEC			= 0x0E,
+	MAX77686_ALARM1_MIN			= 0x0F,
+	MAX77686_ALARM1_HOUR		= 0x10,
+	MAX77686_ALARM1_WEEKDAY		= 0x11,
+	MAX77686_ALARM1_MONTH		= 0x12,
+	MAX77686_ALARM1_YEAR		= 0x13,
+	MAX77686_ALARM1_DATE		= 0x14,
+	MAX77686_ALARM2_SEC			= 0x15,
+	MAX77686_ALARM2_MIN			= 0x16,
+	MAX77686_ALARM2_HOUR		= 0x17,
+	MAX77686_ALARM2_WEEKDAY		= 0x18,
+	MAX77686_ALARM2_MONTH		= 0x19,
+	MAX77686_ALARM2_YEAR		= 0x1A,
+	MAX77686_ALARM2_DATE		= 0x1B,
+};
+
+#define MAX77686_IRQSRC_PMIC	(0)
+#define MAX77686_IRQSRC_RTC		(1 << 0)
+
+#define MAX77686_REG_RAMP_RATE_100MV	(0x3<<6)
+#define MAX77686_REG_RAMP_RATE_55MV		(0x2<<6)
+#define MAX77686_REG_RAMP_RATE_27MV		(0x1<<6)
+#define MAX77686_REG_RAMP_RATE_13MV		(0x0<<6)
+
+enum max77686_irq_source {
+	PMIC_INT1 = 0,
+	PMIC_INT2,
+	RTC_INT,
+
+	MAX77686_IRQ_GROUP_NR,
+};
+
+enum max77686_irq {
+	MAX77686_PMICIRQ_PWRONF,
+	MAX77686_PMICIRQ_PWRONR,
+	MAX77686_PMICIRQ_JIGONBF,
+	MAX77686_PMICIRQ_JIGONBR,
+	MAX77686_PMICIRQ_ACOKBF,
+	MAX77686_PMICIRQ_ACOKBR,
+	MAX77686_PMICIRQ_ONKEY1S,
+	MAX77686_PMICIRQ_MRSTB,
+
+	MAX77686_PMICIRQ_140C,
+	MAX77686_PMICIRQ_120C,
+
+	MAX77686_RTCIRQ_RTC60S,
+	MAX77686_RTCIRQ_RTCA1,
+	MAX77686_RTCIRQ_RTCA2,
+	MAX77686_RTCIRQ_SMPL,
+	MAX77686_RTCIRQ_RTC1S,
+	MAX77686_RTCIRQ_WTSR,
+
+	MAX77686_IRQ_NR,
+};
+
+struct max77686_dev {
+	struct device *dev;
+	struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
+	struct i2c_client *rtc; /* slave addr 0x0c */
+	struct mutex iolock;
+
+	int type;
+
+	int irq;
+	int irq_gpio;
+	int irq_base;
+	bool wakeup;
+	struct mutex irqlock;
+	int irq_masks_cur[MAX77686_IRQ_GROUP_NR];
+	int irq_masks_cache[MAX77686_IRQ_GROUP_NR];
+	int wtsr_smpl;
+
+#ifdef CONFIG_HIBERNATION
+	u8 reg_dump[MAX77686_REG_PMIC_END];
+#endif
+};
+
+enum max77686_types {
+	TYPE_MAX77686,
+};
+
+extern int max77686_irq_init(struct max77686_dev *max77686);
+extern void max77686_irq_exit(struct max77686_dev *max77686);
+extern int max77686_irq_resume(struct max77686_dev *max77686);
+
+extern int max77686_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
+extern int max77686_bulk_read(struct i2c_client *i2c, u8 reg, int count,
+				u8 *buf);
+extern int max77686_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
+extern int max77686_bulk_write(struct i2c_client *i2c, u8 reg, int count,
+				u8 *buf);
+extern int max77686_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
+
+#endif /*  __LINUX_MFD_MAX77686_PRIV_H */
diff --git a/include/linux/mfd/max77686.h b/include/linux/mfd/max77686.h
new file mode 100644
index 0000000..d6ddb93
--- /dev/null
+++ b/include/linux/mfd/max77686.h
@@ -0,0 +1,136 @@
+/*
+ * max77686.h - Driver for the Maxim 77686
+ *
+ *  Copyright (C) 2011 Samsung Electrnoics
+ *  Chiwoong Byun <woong.byun@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * This driver is based on max8997.h
+ *
+ * MAX77686 has PMIC, RTC devices.
+ * The devices share the same I2C bus and included in
+ * this mfd driver.
+ */
+
+#ifndef __LINUX_MFD_MAX77686_H
+#define __LINUX_MFD_MAX77686_H
+
+#include <linux/regulator/consumer.h>
+
+#define MAX77686_SMPL_ENABLE			(0x1)
+#define MAX77686_WTSR_ENABLE			(0x2)
+
+/* MAX77686 regulator IDs */
+enum max77686_regulators {
+	MAX77686_LDO1 = 0,
+	MAX77686_LDO2,
+	MAX77686_LDO3,
+	MAX77686_LDO4,
+	MAX77686_LDO5,
+	MAX77686_LDO6,
+	MAX77686_LDO7,
+	MAX77686_LDO8,
+	MAX77686_LDO9,
+	MAX77686_LDO10,
+	MAX77686_LDO11,
+	MAX77686_LDO12,
+	MAX77686_LDO13,
+	MAX77686_LDO14,
+	MAX77686_LDO15,
+	MAX77686_LDO16,
+	MAX77686_LDO17,
+	MAX77686_LDO18,
+	MAX77686_LDO19,
+	MAX77686_LDO20,
+	MAX77686_LDO21,
+	MAX77686_LDO22,
+	MAX77686_LDO23,
+	MAX77686_LDO24,
+	MAX77686_LDO25,
+	MAX77686_LDO26,
+	MAX77686_BUCK1,
+	MAX77686_BUCK2,
+	MAX77686_BUCK3,
+	MAX77686_BUCK4,
+	MAX77686_BUCK5,
+	MAX77686_BUCK6,
+	MAX77686_BUCK7,
+	MAX77686_BUCK8,
+	MAX77686_BUCK9,
+	MAX77686_EN32KHZ_AP,
+	MAX77686_EN32KHZ_CP,
+	MAX77686_P32KH,
+
+	MAX77686_REG_MAX,
+};
+
+struct max77686_regulator_data {
+	int id;
+	struct regulator_init_data *initdata;
+};
+
+enum max77686_opmode {
+	MAX77686_OPMODE_NORMAL,
+	MAX77686_OPMODE_LP,
+	MAX77686_OPMODE_STANDBY,
+};
+
+enum max77686_ramp_rate {
+	MAX77686_RAMP_RATE_100MV,
+	MAX77686_RAMP_RATE_13MV,
+	MAX77686_RAMP_RATE_27MV,
+	MAX77686_RAMP_RATE_55MV,
+};
+
+struct max77686_opmode_data {
+	int id;
+	int mode;
+};
+
+struct max77686_buck234_gpio_data {
+	int gpio;
+	int data;
+};
+
+struct max77686_platform_data {
+	/* IRQ */
+	int irq_gpio;
+	int irq_base;
+	int ono;
+	int wakeup;
+
+	/* ---- PMIC ---- */
+	struct max77686_regulator_data *regulators;
+	int num_regulators;
+	int has_full_constraints;
+
+	struct max77686_opmode_data *opmode_data;
+	int ramp_rate;
+	int wtsr_smpl;
+
+	/*
+	 * GPIO-DVS feature is not enabled with the current version of
+	 * MAX77686 driver. Buck2/3/4_voltages[0] is used as the default
+	 * voltage at probe. DVS/SELB gpios are set as OUTPUT-LOW.
+	 */
+	struct max77686_buck234_gpio_data buck234_gpio_dvs[3]; /* GPIO of [0]DVS1, [1]DVS2, [2]DVS3 */
+	int buck234_gpio_selb[3]; /* [0]SELB2, [1]SELB3, [2]SELB4 */
+	unsigned int buck2_voltage[8]; /* buckx_voltage in uV */
+	unsigned int buck3_voltage[8];
+	unsigned int buck4_voltage[8];
+};
+
+#endif /* __LINUX_MFD_MAX77686_H */
diff --git a/include/linux/mfd/max77693-private.h b/include/linux/mfd/max77693-private.h
new file mode 100644
index 0000000..ff0b1a2
--- /dev/null
+++ b/include/linux/mfd/max77693-private.h
@@ -0,0 +1,406 @@
+/*
+ * max77693-private.h - Voltage regulator driver for the Maxim 77693
+ *
+ *  Copyright (C) 2011 Samsung Electrnoics
+ *  SangYoung Son <hello.son@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_MFD_MAX77693_PRIV_H
+#define __LINUX_MFD_MAX77693_PRIV_H
+
+#include <linux/i2c.h>
+
+#define MAX77693_NUM_IRQ_MUIC_REGS	3
+#define MAX77693_REG_INVALID		(0xff)
+
+#define MAX77693_IRQSRC_CHG		(1 << 0)
+#define MAX77693_IRQSRC_TOP		(1 << 1)
+#define MAX77693_IRQSRC_FLASH		(1 << 2)
+#define MAX77693_IRQSRC_MUIC		(1 << 3)
+
+/* pmic revision */
+enum max77693_pmic_rev {
+	MAX77693_REV_PASS1	= 0x00,
+	MAX77693_REV_PASS2	= 0x01,
+	MAX77693_REV_PASS3	= 0x02,
+};
+
+/* Slave addr = 0xCC: Charger, Flash LED, Haptic */
+enum max77693_pmic_reg {
+	MAX77693_LED_REG_IFLASH1			= 0x00,
+	MAX77693_LED_REG_IFLASH2			= 0x01,
+	MAX77693_LED_REG_ITORCH				= 0x02,
+	MAX77693_LED_REG_ITORCHTORCHTIMER		= 0x03,
+	MAX77693_LED_REG_FLASH_TIMER			= 0x04,
+	MAX77693_LED_REG_FLASH_EN			= 0x05,
+	MAX77693_LED_REG_MAX_FLASH1			= 0x06,
+	MAX77693_LED_REG_MAX_FLASH2			= 0x07,
+	MAX77693_LED_REG_MAX_FLASH3			= 0x08,
+	MAX77693_LED_REG_MAX_FLASH4			= 0x09,
+	MAX77693_LED_REG_VOUT_CNTL			= 0x0A,
+	MAX77693_LED_REG_VOUT_FLASH1			= 0x0B,
+	MAX77693_LED_REG_VOUT_FLASH2			= 0x0C,
+	MAX77693_LED_REG_RESERVED_0D			= 0x0D,
+	MAX77693_LED_REG_FLASH_INT			= 0x0E,
+	MAX77693_LED_REG_FLASH_INT_MASK			= 0x0F,
+	MAX77693_LED_REG_FLASH_INT_STATUS		= 0x10,
+	MAX77693_LED_REG_RESERVED_11			= 0x11,
+
+	MAX77693_PMIC_REG_PMIC_ID1			= 0x20,
+	MAX77693_PMIC_REG_PMIC_ID2			= 0x21,
+	MAX77693_PMIC_REG_INTSRC			= 0x22,
+	MAX77693_PMIC_REG_INTSRC_MASK			= 0x23,
+	MAX77693_PMIC_REG_TOPSYS_INT			= 0x24,
+	MAX77693_PMIC_REG_RESERVED_25			= 0x25,
+	MAX77693_PMIC_REG_TOPSYS_INT_MASK		= 0x26,
+	MAX77693_PMIC_REG_RESERVED_27			= 0x27,
+	MAX77693_PMIC_REG_TOPSYS_STAT			= 0x28,
+	MAX77693_PMIC_REG_RESERVED_29			= 0x29,
+	MAX77693_PMIC_REG_MAINCTRL1			= 0x2A,
+	MAX77693_PMIC_REG_LSCNFG			= 0x2B,
+	MAX77693_PMIC_REG_RESERVED_2C			= 0x2C,
+	MAX77693_PMIC_REG_RESERVED_2D			= 0x2D,
+
+	MAX77693_CHG_REG_CHG_INT			= 0xB0,
+	MAX77693_CHG_REG_CHG_INT_MASK			= 0xB1,
+	MAX77693_CHG_REG_CHG_INT_OK			= 0xB2,
+	MAX77693_CHG_REG_CHG_DTLS_00			= 0xB3,
+	MAX77693_CHG_REG_CHG_DTLS_01			= 0xB4,
+	MAX77693_CHG_REG_CHG_DTLS_02			= 0xB5,
+	MAX77693_CHG_REG_CHG_DTLS_03			= 0xB6,
+	MAX77693_CHG_REG_CHG_CNFG_00			= 0xB7,
+	MAX77693_CHG_REG_CHG_CNFG_01			= 0xB8,
+	MAX77693_CHG_REG_CHG_CNFG_02			= 0xB9,
+	MAX77693_CHG_REG_CHG_CNFG_03			= 0xBA,
+	MAX77693_CHG_REG_CHG_CNFG_04			= 0xBB,
+	MAX77693_CHG_REG_CHG_CNFG_05			= 0xBC,
+	MAX77693_CHG_REG_CHG_CNFG_06			= 0xBD,
+	MAX77693_CHG_REG_CHG_CNFG_07			= 0xBE,
+	MAX77693_CHG_REG_CHG_CNFG_08			= 0xBF,
+	MAX77693_CHG_REG_CHG_CNFG_09			= 0xC0,
+	MAX77693_CHG_REG_CHG_CNFG_10			= 0xC1,
+	MAX77693_CHG_REG_CHG_CNFG_11			= 0xC2,
+	MAX77693_CHG_REG_CHG_CNFG_12			= 0xC3,
+	MAX77693_CHG_REG_CHG_CNFG_13			= 0xC4,
+	MAX77693_CHG_REG_CHG_CNFG_14			= 0xC5,
+	MAX77693_CHG_REG_SAFEOUT_CTRL			= 0xC6,
+
+	MAX77693_PMIC_REG_END,
+};
+
+/* Slave addr = 0x4A: MUIC */
+enum max77693_muic_reg {
+	MAX77693_MUIC_REG_ID		= 0x00,
+	MAX77693_MUIC_REG_INT1		= 0x01,
+	MAX77693_MUIC_REG_INT2		= 0x02,
+	MAX77693_MUIC_REG_INT3		= 0x03,
+	MAX77693_MUIC_REG_STATUS1	= 0x04,
+	MAX77693_MUIC_REG_STATUS2	= 0x05,
+	MAX77693_MUIC_REG_STATUS3	= 0x06,
+	MAX77693_MUIC_REG_INTMASK1	= 0x07,
+	MAX77693_MUIC_REG_INTMASK2	= 0x08,
+	MAX77693_MUIC_REG_INTMASK3	= 0x09,
+	MAX77693_MUIC_REG_CDETCTRL1	= 0x0A,
+	MAX77693_MUIC_REG_CDETCTRL2	= 0x0B,
+	MAX77693_MUIC_REG_CTRL1		= 0x0C,
+	MAX77693_MUIC_REG_CTRL2		= 0x0D,
+	MAX77693_MUIC_REG_CTRL3		= 0x0E,
+
+	MAX77693_MUIC_REG_END,
+};
+
+/* Slave addr = 0x90: Haptic */
+enum max77693_haptic_reg {
+	MAX77693_HAPTIC_REG_STATUS		= 0x00,
+	MAX77693_HAPTIC_REG_CONFIG1		= 0x01,
+	MAX77693_HAPTIC_REG_CONFIG2		= 0x02,
+	MAX77693_HAPTIC_REG_CONFIG_CHNL		= 0x03,
+	MAX77693_HAPTIC_REG_CONFG_CYC1		= 0x04,
+	MAX77693_HAPTIC_REG_CONFG_CYC2		= 0x05,
+	MAX77693_HAPTIC_REG_CONFIG_PER1		= 0x06,
+	MAX77693_HAPTIC_REG_CONFIG_PER2		= 0x07,
+	MAX77693_HAPTIC_REG_CONFIG_PER3		= 0x08,
+	MAX77693_HAPTIC_REG_CONFIG_PER4		= 0x09,
+	MAX77693_HAPTIC_REG_CONFIG_DUTY1	= 0x0A,
+	MAX77693_HAPTIC_REG_CONFIG_DUTY2	= 0x0B,
+	MAX77693_HAPTIC_REG_CONFIG_PWM1		= 0x0C,
+	MAX77693_HAPTIC_REG_CONFIG_PWM2		= 0x0D,
+	MAX77693_HAPTIC_REG_CONFIG_PWM3		= 0x0E,
+	MAX77693_HAPTIC_REG_CONFIG_PWM4		= 0x0F,
+	MAX77693_HAPTIC_REG_REV			= 0x10,
+
+	MAX77693_HAPTIC_REG_END,
+};
+
+/* MAX77693 REGISTER ENABLE or DISABLE bit */
+#define MAX77693_ENABLE_BIT 1
+#define MAX77693_DISABLE_BIT 0
+
+/* MAX77693 CHG_CNFG_00 register */
+#define CHG_CNFG_00_MODE_SHIFT		0
+#define CHG_CNFG_00_CHG_SHIFT		0
+#define CHG_CNFG_00_OTG_SHIFT		1
+#define CHG_CNFG_00_BUCK_SHIFT		2
+#define CHG_CNFG_00_BOOST_SHIFT		3
+#define CHG_CNFG_00_DIS_MUIC_CTRL_SHIFT	5
+#define CHG_CNFG_00_MODE_MASK		(0xf << CHG_CNFG_00_MODE_SHIFT)
+#define CHG_CNFG_00_CHG_MASK		(1 << CHG_CNFG_00_CHG_SHIFT)
+#define CHG_CNFG_00_OTG_MASK		(1 << CHG_CNFG_00_OTG_SHIFT)
+#define CHG_CNFG_00_BUCK_MASK		(1 << CHG_CNFG_00_BUCK_SHIFT)
+#define CHG_CNFG_00_BOOST_MASK		(1 << CHG_CNFG_00_BOOST_SHIFT)
+#define CHG_CNFG_00_DIS_MUIC_CTRL_MASK	(1 << CHG_CNFG_00_DIS_MUIC_CTRL_SHIFT)
+
+/* MAX77693 STATUS1 register */
+#define STATUS1_ADC_SHIFT		0
+#define STATUS1_ADCLOW_SHIFT		5
+#define STATUS1_ADCERR_SHIFT		6
+#define STATUS1_ADC1K_SHIFT		7
+#define STATUS1_ADC_MASK		(0x1f << STATUS1_ADC_SHIFT)
+#define STATUS1_ADCLOW_MASK		(0x1 << STATUS1_ADCLOW_SHIFT)
+#define STATUS1_ADCERR_MASK		(0x1 << STATUS1_ADCERR_SHIFT)
+#define STATUS1_ADC1K_MASK		(0x1 << STATUS1_ADC1K_SHIFT)
+
+/* MAX77693 STATUS2 register */
+#define STATUS2_CHGTYP_SHIFT		0
+#define STATUS2_CHGDETRUN_SHIFT		3
+#define STATUS2_VBVOLT_SHIFT		6
+#define STATUS2_CHGTYP_MASK		(0x7 << STATUS2_CHGTYP_SHIFT)
+#define STATUS2_CHGDETRUN_MASK		(0x1 << STATUS2_CHGDETRUN_SHIFT)
+#define STATUS2_VBVOLT_MASK		(0x1 << STATUS2_VBVOLT_SHIFT)
+
+/* MAX77693 CDETCTRL1 register */
+#define CHGDETEN_SHIFT			0
+#define CHGTYPM_SHIFT			1
+#define CHGDETEN_MASK			(0x1 << CHGDETEN_SHIFT)
+#define CHGTYPM_MASK			(0x1 << CHGTYPM_SHIFT)
+
+/* MAX77693 CONTROL1 register */
+#define CLEAR_IDBEN_MICEN_MASK	0x3f
+#define COMN1SW_SHIFT				0x0
+#define COMP2SW_SHIFT				0x3
+#define MICEN_SHIFT					0x6
+#define COMN1SW_MASK				(0x7 << COMN1SW_SHIFT)
+#define COMP2SW_MASK				(0x7 << COMP2SW_SHIFT)
+#define MICEN_MASK					(0x1 << MICEN_SHIFT)
+
+/* MAX77693 CONTROL2 register */
+#define CTRL2_ACCDET_SHIFT		5
+#define CTRL2_ACCDET_MASK		(0x1 << CTRL2_ACCDET_SHIFT)
+#define CTRL2_CPEn_SHIFT		2
+#define CTRL2_CPEn_MASK		(0x1 << CTRL2_CPEn_SHIFT)
+#define CTRL2_LOWPWD_SHIFT		0
+#define CTRL2_LOWPWD_MASK		(0x1 << CTRL2_LOWPWD_SHIFT)
+#define CTRL2_CPEn1_LOWPWD0 ((MAX77693_ENABLE_BIT << CTRL2_CPEn_SHIFT) | \
+				(MAX77693_DISABLE_BIT << CTRL2_LOWPWD_SHIFT))
+#define CTRL2_CPEn0_LOWPWD1 ((MAX77693_DISABLE_BIT << CTRL2_CPEn_SHIFT) | \
+				(MAX77693_ENABLE_BIT << CTRL2_LOWPWD_SHIFT))
+
+/* MAX77693 CONTROL3 register */
+#define CTRL3_JIGSET_SHIFT		0
+#define CTRL3_BOOTSET_SHIFT		2
+#define CTRL3_ADCDBSET_SHIFT		4
+#define CTRL3_JIGSET_MASK		(0x3 << CTRL3_JIGSET_SHIFT)
+#define CTRL3_BOOTSET_MASK		(0x3 << CTRL3_BOOTSET_SHIFT)
+#define CTRL3_ADCDBSET_MASK		(0x3 << CTRL3_ADCDBSET_SHIFT)
+
+/* Interrupt 1 */
+#define INT_DETACH		(0x1 << 1)
+#define INT_ATTACH		(0x1 << 0)
+
+/* muic register value for COMN1, COMN2 in CTRL1 reg  */
+enum max77693_reg_ctrl1_val {
+	MAX77693_MUIC_CTRL1_BIN_0_000 = 0x00,
+	MAX77693_MUIC_CTRL1_BIN_1_001 = 0x01,
+	MAX77693_MUIC_CTRL1_BIN_2_010 = 0x02,
+	MAX77693_MUIC_CTRL1_BIN_3_011 = 0x03,
+	MAX77693_MUIC_CTRL1_BIN_4_100 = 0x04,
+	MAX77693_MUIC_CTRL1_BIN_5_101 = 0x05,
+	MAX77693_MUIC_CTRL1_BIN_6_110 = 0x06,
+	MAX77693_MUIC_CTRL1_BIN_7_111 = 0x07,
+};
+
+enum max77693_switch_sel_val {
+	MAX77693_SWITCH_SEL_1st_BIT_USB		= 0x1 << 0,
+	MAX77693_SWITCH_SEL_2nd_BIT_UART	= 0x1 << 1,
+#ifdef CONFIG_LTE_VIA_SWITCH
+	MAX77693_SWITCH_SEL_3rd_BIT_LTE_UART	= 0x1 << 2,
+#endif
+};
+
+enum max77693_reg_ctrl1_type {
+	CTRL1_AP_USB =
+		(MAX77693_MUIC_CTRL1_BIN_1_001 << COMP2SW_SHIFT)
+		| MAX77693_MUIC_CTRL1_BIN_1_001 ,
+	CTRL1_AUDIO =
+		(MAX77693_MUIC_CTRL1_BIN_2_010 << COMP2SW_SHIFT)
+		| MAX77693_MUIC_CTRL1_BIN_2_010 ,
+	CTRL1_CP_USB =
+		(MAX77693_MUIC_CTRL1_BIN_4_100 << COMP2SW_SHIFT)
+		| MAX77693_MUIC_CTRL1_BIN_4_100 ,
+	CTRL1_AP_UART =
+		(MAX77693_MUIC_CTRL1_BIN_3_011 << COMP2SW_SHIFT)
+		| MAX77693_MUIC_CTRL1_BIN_3_011 ,
+	CTRL1_CP_UART =
+		(MAX77693_MUIC_CTRL1_BIN_5_101 << COMP2SW_SHIFT)
+		| MAX77693_MUIC_CTRL1_BIN_5_101 ,
+};
+/*TODO must modify H/W rev.5*/
+
+enum max77693_irq_source {
+	LED_INT = 0,
+	TOPSYS_INT,
+	CHG_INT,
+	MUIC_INT1,
+	MUIC_INT2,
+	MUIC_INT3,
+
+	MAX77693_IRQ_GROUP_NR,
+};
+
+enum max77693_irq {
+	/* PMIC; FLASH */
+	MAX77693_LED_IRQ_FLED2_OPEN,
+	MAX77693_LED_IRQ_FLED2_SHORT,
+	MAX77693_LED_IRQ_FLED1_OPEN,
+	MAX77693_LED_IRQ_FLED1_SHORT,
+	MAX77693_LED_IRQ_MAX_FLASH,
+
+	/* PMIC; TOPSYS */
+	MAX77693_TOPSYS_IRQ_T120C_INT,
+	MAX77693_TOPSYS_IRQ_T140C_INT,
+	MAX77693_TOPSYS_IRQLOWSYS_INT,
+
+	/* PMIC; Charger */
+	MAX77693_CHG_IRQ_BYP_I,
+	MAX77693_CHG_IRQ_THM_I,
+	MAX77693_CHG_IRQ_BAT_I,
+	MAX77693_CHG_IRQ_CHG_I,
+	MAX77693_CHG_IRQ_CHGIN_I,
+
+	/* MUIC INT1 */
+	MAX77693_MUIC_IRQ_INT1_ADC,
+	MAX77693_MUIC_IRQ_INT1_ADCLOW,
+	MAX77693_MUIC_IRQ_INT1_ADCERR,
+	MAX77693_MUIC_IRQ_INT1_ADC1K,
+
+	/* MUIC INT2 */
+	MAX77693_MUIC_IRQ_INT2_CHGTYP,
+	MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
+	MAX77693_MUIC_IRQ_INT2_DCDTMR,
+	MAX77693_MUIC_IRQ_INT2_DXOVP,
+	MAX77693_MUIC_IRQ_INT2_VBVOLT,
+	MAX77693_MUIC_IRQ_INT2_VIDRM,
+
+	/* MUIC INT3 */
+	MAX77693_MUIC_IRQ_INT3_EOC,
+	MAX77693_MUIC_IRQ_INT3_CGMBC,
+	MAX77693_MUIC_IRQ_INT3_OVP,
+	MAX77693_MUIC_IRQ_INT3_MBCCHGERR,
+	MAX77693_MUIC_IRQ_INT3_CHGENABLED,
+	MAX77693_MUIC_IRQ_INT3_BATDET,
+
+	MAX77693_IRQ_NR,
+};
+
+struct max77693_dev {
+	struct device *dev;
+	struct i2c_client *i2c; /* 0xCC; Charger, Flash LED */
+	struct i2c_client *muic; /* 0x4A; MUIC */
+	struct i2c_client *haptic; /* 0x90; Haptic */
+	struct mutex iolock;
+
+	int type;
+
+	int irq;
+	int irq_base;
+	int irq_gpio;
+	bool wakeup;
+	struct mutex irqlock;
+	int irq_masks_cur[MAX77693_IRQ_GROUP_NR];
+	int irq_masks_cache[MAX77693_IRQ_GROUP_NR];
+
+#ifdef CONFIG_HIBERNATION
+	/* For hibernation */
+	u8 reg_pmic_dump[MAX77693_PMIC_REG_END];
+	u8 reg_muic_dump[MAX77693_MUIC_REG_END];
+	u8 reg_haptic_dump[MAX77693_HAPTIC_REG_END];
+#endif
+
+	/* pmic revision */
+	u8 pmic_rev;	/* REV */
+	u8 pmic_ver;	/* VERSION */
+};
+
+enum max77693_types {
+	TYPE_MAX77693,
+};
+
+extern struct device *switch_dev;
+extern int max77693_irq_init(struct max77693_dev *max77693);
+extern void max77693_irq_exit(struct max77693_dev *max77693);
+extern int max77693_irq_resume(struct max77693_dev *max77693);
+
+extern int max77693_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
+extern int max77693_bulk_read(struct i2c_client *i2c, u8 reg, int count,
+				u8 *buf);
+extern int max77693_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
+extern int max77693_bulk_write(struct i2c_client *i2c, u8 reg, int count,
+				u8 *buf);
+extern int max77693_update_reg(struct i2c_client *i2c,
+				u8 reg, u8 val, u8 mask);
+extern int max77693_muic_get_charging_type(void);
+extern int max77693_muic_get_status1_adc1k_value(void);
+extern int max77693_muic_get_status1_adc_value(void);
+extern void otg_control(int);
+extern void powered_otg_control(int);
+extern int max77693_muic_set_audio_switch(bool enable);
+
+#ifdef CONFIG_MFD_MAX77693
+enum cable_type_muic {
+	CABLE_TYPE_NONE_MUIC = 0,
+	CABLE_TYPE_USB_MUIC,
+	CABLE_TYPE_OTG_MUIC,
+	CABLE_TYPE_TA_MUIC,
+	CABLE_TYPE_DESKDOCK_MUIC,
+	CABLE_TYPE_CARDOCK_MUIC,
+	CABLE_TYPE_JIG_UART_OFF_MUIC,
+	CABLE_TYPE_JIG_UART_OFF_VB_MUIC,	/* VBUS enabled */
+	CABLE_TYPE_JIG_UART_ON_MUIC,
+	CABLE_TYPE_JIG_USB_OFF_MUIC,
+	CABLE_TYPE_JIG_USB_ON_MUIC,
+	CABLE_TYPE_MHL_MUIC,
+	CABLE_TYPE_MHL_VB_MUIC,
+	CABLE_TYPE_SMARTDOCK_MUIC,
+	CABLE_TYPE_UNKNOWN_MUIC
+};
+
+enum {
+	AP_USB_MODE = 0,
+	CP_USB_MODE,
+	AUDIO_MODE,
+};
+
+enum {
+	UART_PATH_CP = 0,
+	UART_PATH_AP,
+#ifdef CONFIG_LTE_VIA_SWITCH
+	UART_PATH_LTE,
+#endif
+};
+#endif /* CONFIG_MFD_MAX77693 */
+
+#endif /*  __LINUX_MFD_MAX77693_PRIV_H */
diff --git a/include/linux/mfd/max77693.h b/include/linux/mfd/max77693.h
new file mode 100644
index 0000000..07f2162
--- /dev/null
+++ b/include/linux/mfd/max77693.h
@@ -0,0 +1,141 @@
+/*
+ * max77693.h - Driver for the Maxim 77693
+ *
+ *  Copyright (C) 2011 Samsung Electrnoics
+ *  SangYoung Son <hello.son@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * This driver is based on max8997.h
+ *
+ * MAX77693 has Charger, Flash LED, Haptic, MUIC devices.
+ * The devices share the same I2C bus and included in
+ * this mfd driver.
+ */
+
+#ifndef __LINUX_MFD_MAX77693_H
+#define __LINUX_MFD_MAX77693_H
+
+#include <linux/regulator/consumer.h>
+
+enum {
+	MAX77693_MUIC_DETACHED = 0,
+	MAX77693_MUIC_ATTACHED
+};
+
+/* MAX77686 regulator IDs */
+enum max77693_regulators {
+	MAX77693_ESAFEOUT1 = 0,
+	MAX77693_ESAFEOUT2,
+
+	MAX77693_CHARGER,
+
+	MAX77693_REG_MAX,
+};
+
+struct max77693_charger_reg_data {
+	u8 addr;
+	u8 data;
+};
+
+struct max77693_charger_platform_data {
+	struct max77693_charger_reg_data *init_data;
+	int num_init_data;
+#ifdef CONFIG_BATTERY_WPC_CHARGER
+	int wpc_irq_gpio;
+	int vbus_irq_gpio;
+	bool wc_pwr_det;
+#endif
+};
+
+#ifdef CONFIG_VIBETONZ
+#define MAX8997_MOTOR_REG_CONFIG2	0x2
+#define MOTOR_LRA			(1<<7)
+#define MOTOR_EN			(1<<6)
+#define EXT_PWM				(0<<5)
+#define DIVIDER_128			(1<<1)
+
+struct max77693_haptic_platform_data {
+	u16 max_timeout;
+	u16 duty;
+	u16 period;
+	u16 reg2;
+	char *regulator_name;
+	unsigned int pwm_id;
+
+	void (*init_hw) (void);
+	void (*motor_en) (bool);
+};
+#endif
+
+#ifdef CONFIG_LEDS_MAX77693
+struct max77693_led_platform_data;
+#endif
+
+struct max77693_regulator_data {
+	int id;
+	struct regulator_init_data *initdata;
+};
+
+struct max77693_platform_data {
+	/* IRQ */
+	int irq_base;
+	int irq_gpio;
+	int wakeup;
+	struct max77693_muic_data *muic;
+	bool (*is_default_uart_path_cp) (void);
+	struct max77693_regulator_data *regulators;
+	int num_regulators;
+#ifdef CONFIG_VIBETONZ
+	/* haptic motor data */
+	struct max77693_haptic_platform_data *haptic_data;
+#endif
+#ifdef CONFIG_LEDS_MAX77693
+	/* led (flash/torch) data */
+	struct max77693_led_platform_data *led_data;
+#endif
+#ifdef CONFIG_BATTERY_MAX77693_CHARGER
+	/* charger data */
+	struct max77693_charger_platform_data *charger_data;
+#endif
+};
+
+enum cable_type_muic;
+struct max77693_muic_data {
+	void (*usb_cb) (u8 attached);
+	void (*uart_cb) (u8 attached);
+	int (*charger_cb) (enum cable_type_muic);
+	void (*deskdock_cb) (bool attached);
+	void (*cardock_cb) (bool attached);
+	void (*mhl_cb) (int attached);
+	void (*init_cb) (void);
+	int (*set_safeout) (int path);
+	 bool(*is_mhl_attached) (void);
+	int (*cfg_uart_gpio) (void);
+	void (*jig_uart_cb) (int path);
+	int (*host_notify_cb) (int enable);
+	int gpio_usb_sel;
+	int sw_path;
+	int uart_path;
+
+	void (*jig_state) (int jig_state);
+
+};
+
+#if defined(CONFIG_MACH_M0_CTC)
+int max7693_muic_cp_usb_state(void);
+#endif
+
+#endif				/* __LINUX_MFD_MAX77693_H */
diff --git a/include/linux/mfd/max8698-private.h b/include/linux/mfd/max8698-private.h
new file mode 100644
index 0000000..332b04c
--- /dev/null
+++ b/include/linux/mfd/max8698-private.h
@@ -0,0 +1,117 @@
+/*
+ * max8698.h - Voltage regulator driver for the Maxim 8698
+ *
+ *  Copyright (C) 2009-2010 Samsung Electrnoics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *  Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  2010.10.25
+ *  Modified by Taekki Kim <taekki.kim@samsung.com>
+ */
+
+#ifndef __LINUX_MFD_MAX8698_PRIV_H
+#define __LINUX_MFD_MAX8698_PRIV_H
+
+/* MAX 8698 registers */
+enum {
+	MAX8698_REG_ONOFF1,
+	MAX8698_REG_ONOFF2,
+	MAX8698_REG_ADISCHG_EN1,
+	MAX8698_REG_ADISCHG_EN2,
+	MAX8698_REG_DVSARM12,
+	MAX8698_REG_DVSARM34,
+	MAX8698_REG_DVSINT12,
+	MAX8698_REG_BUCK3,
+	MAX8698_REG_LDO2_LDO3,
+	MAX8698_REG_LDO4,
+	MAX8698_REG_LDO5,
+	MAX8698_REG_LDO6,
+	MAX8698_REG_LDO7,
+	MAX8698_REG_LDO8_BKCHAR,
+	MAX8698_REG_LDO9,
+	MAX8698_REG_LBCNFG,
+};
+
+/* ONOFF1 */
+#define MAX8698_SHIFT_EN1	7
+#define MAX8698_SHIFT_EN2	6
+#define MAX8698_SHIFT_EN3	5
+#define MAX8698_SHIFT_ELDO2	4
+#define MAX8698_SHIFT_ELDO3	3
+#define MAX8698_SHIFT_ELDO4	2
+#define MAX8698_SHIFT_ELDO5	1
+
+#define MAX8698_MASK_EN1	(0x1 << MAX8698_SHIFT_EN1)
+#define MAX8698_MASK_EN2	(0x1 << MAX8698_SHIFT_EN2)
+#define MAX8698_MASK_EN3	(0x1 << MAX8698_SHIFT_EN3)
+#define MAX8698_MASK_ELDO2	(0x1 << MAX8698_SHIFT_ELDO2)
+#define MAX8698_MASK_ELDO3	(0x1 << MAX8698_SHIFT_ELDO3)
+#define MAX8698_MASK_ELDO4	(0x1 << MAX8698_SHIFT_ELDO4)
+#define MAX8698_MASK_ELDO5	(0x1 << MAX8698_SHIFT_ELDO5)
+
+/* ONOFF2 */
+#define MAX8698_SHIFT_ELDO6	7
+#define MAX8698_SHIFT_ELDO7	6
+#define MAX8698_SHIFT_ELDO8	5
+#define MAX8698_SHIFT_ELDO9	4
+#define MAX8698_SHIFT_ELBCNFG	0
+
+#define MAX8698_MASK_ELDO6	(0x1 << MAX8698_SHIFT_ELDO6)
+#define MAX8698_MASK_ELDO7	(0x1 << MAX8698_SHIFT_ELDO7)
+#define MAX8698_MASK_ELDO8	(0x1 << MAX8698_SHIFT_ELDO8)
+#define MAX8698_MASK_ELDO9	(0x1 << MAX8698_SHIFT_ELDO9)
+#define MAX8698_MASK_ELBCNFG	(0x1 << MAX8698_SHIFT_ELBCNFG)
+
+
+/**
+ * struct max8698_dev - max8698 master device for sub-drivers
+ * @dev: master device of the chip (can be used to access platform data)
+ * @i2c_client: i2c client private data
+ * @dev_read():	chip register read function
+ * @dev_write(): chip register write function
+ * @dev_update(): chip register update function
+ * @iolock: mutex for serializing io access
+ */
+
+struct max8698_dev {
+	struct device *dev;
+	struct i2c_client *i2c_client;
+	int (*dev_read)(struct max8698_dev *max8698, u8 reg, u8 *dest);
+	int (*dev_write)(struct max8698_dev *max8698, u8 reg, u8 val);
+	int (*dev_update)(struct max8698_dev *max8698, u8 reg, u8 val, u8 mask);
+	struct mutex iolock;
+};
+
+static inline int max8698_read_reg(struct max8698_dev *max8698, u8 reg,
+				   u8 *value)
+{
+	return max8698->dev_read(max8698, reg, value);
+}
+
+static inline int max8698_write_reg(struct max8698_dev *max8698, u8 reg,
+				    u8 value)
+{
+	return max8698->dev_write(max8698, reg, value);
+}
+
+static inline int max8698_update_reg(struct max8698_dev *max8698, u8 reg,
+				     u8 value, u8 mask)
+{
+	return max8698->dev_update(max8698, reg, value, mask);
+}
+
+#endif /*  __LINUX_MFD_MAX8698_PRIV_H */
diff --git a/include/linux/mfd/max8698.h b/include/linux/mfd/max8698.h
new file mode 100644
index 0000000..9a1b52a
--- /dev/null
+++ b/include/linux/mfd/max8698.h
@@ -0,0 +1,78 @@
+/*
+ * max8698.h - Voltage regulator driver for the Maxim 8698
+ *
+ *  Copyright (C) 2009-2010 Samsung Electrnoics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *  Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  2010.10.25
+ *  Modified by Taekki Kim <taekki.kim@samsung.com>
+ */
+
+#ifndef __LINUX_MFD_MAX8698_H
+#define __LINUX_MFD_MAX8698_H
+
+#include <linux/regulator/machine.h>
+
+/* MAX 8698 regulator ids */
+enum {
+	MAX8698_LDO1 = 1,
+	MAX8698_LDO2,
+	MAX8698_LDO3,
+	MAX8698_LDO4,
+	MAX8698_LDO5,
+	MAX8698_LDO6,
+	MAX8698_LDO7,
+	MAX8698_LDO8,
+	MAX8698_LDO9,
+	MAX8698_BUCK1,
+	MAX8698_BUCK2,
+	MAX8698_BUCK3,
+};
+
+/**
+ * max8698_regulator_data - regulator data
+ * @id: regulator id
+ * @initdata: regulator init data (contraints, supplies, ...)
+ */
+struct max8698_regulator_data {
+	int				id;
+	struct regulator_init_data	*initdata;
+};
+
+/**
+ * struct max8698_board - packages regulator init data
+ * @num_regulators: number of regultors used
+ * @regulators: array of defined regulators
+ */
+
+struct max8698_platform_data {
+	int				num_regulators;
+	struct max8698_regulator_data	*regulators;
+
+       int		dvsarm1;
+       int		dvsarm2;
+       int		dvsarm3;
+       int		dvsarm4;
+       int		dvsint1;
+       int		dvsint2;
+       int		set1;
+       int		set2;
+       int		set3;
+};
+
+#endif /*  __LINUX_MFD_MAX8698_H */
diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
index 5ff2400..ca61419 100644
--- a/include/linux/mfd/max8997-private.h
+++ b/include/linux/mfd/max8997-private.h
@@ -1,8 +1,9 @@
 /*
- * max8997.h - Voltage regulator driver for the Maxim 8997
+ * max8997-private.h - Voltage regulator driver for the Maxim 8997
  *
- *  Copyright (C) 2010 Samsung Electrnoics
- *  MyungJoo Ham <myungjoo.ham@samsung.com>
+ *  Copyright (C) 2009-2010 Samsung Electrnoics
+ *
+ *  based on max8998-private.h
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,343 +23,386 @@
 #ifndef __LINUX_MFD_MAX8997_PRIV_H
 #define __LINUX_MFD_MAX8997_PRIV_H
 
-#include <linux/i2c.h>
-
-#define MAX8997_REG_INVALID	(0xff)
+#define MAX8997_NUM_IRQ_PMIC_REGS	4
+#define MAX8997_NUM_IRQ_MUIC_REGS	3
+#define MAX8997_NUM_IRQ_REGS		(MAX8997_NUM_IRQ_PMIC_REGS +\
+					 MAX8997_NUM_IRQ_MUIC_REGS)
 
+/* MAX 8997 PMIC registers */
 enum max8997_pmic_reg {
-	MAX8997_REG_PMIC_ID0	= 0x00,
-	MAX8997_REG_PMIC_ID1	= 0x01,
-	MAX8997_REG_INTSRC	= 0x02,
-	MAX8997_REG_INT1	= 0x03,
-	MAX8997_REG_INT2	= 0x04,
-	MAX8997_REG_INT3	= 0x05,
-	MAX8997_REG_INT4	= 0x06,
-
-	MAX8997_REG_INT1MSK	= 0x08,
-	MAX8997_REG_INT2MSK	= 0x09,
-	MAX8997_REG_INT3MSK	= 0x0a,
-	MAX8997_REG_INT4MSK	= 0x0b,
-
-	MAX8997_REG_STATUS1	= 0x0d,
-	MAX8997_REG_STATUS2	= 0x0e,
-	MAX8997_REG_STATUS3	= 0x0f,
-	MAX8997_REG_STATUS4	= 0x10,
-
-	MAX8997_REG_MAINCON1	= 0x13,
-	MAX8997_REG_MAINCON2	= 0x14,
-	MAX8997_REG_BUCKRAMP	= 0x15,
-
-	MAX8997_REG_BUCK1CTRL	= 0x18,
-	MAX8997_REG_BUCK1DVS1	= 0x19,
-	MAX8997_REG_BUCK1DVS2	= 0x1a,
-	MAX8997_REG_BUCK1DVS3	= 0x1b,
-	MAX8997_REG_BUCK1DVS4	= 0x1c,
-	MAX8997_REG_BUCK1DVS5	= 0x1d,
-	MAX8997_REG_BUCK1DVS6	= 0x1e,
-	MAX8997_REG_BUCK1DVS7	= 0x1f,
-	MAX8997_REG_BUCK1DVS8	= 0x20,
-	MAX8997_REG_BUCK2CTRL	= 0x21,
-	MAX8997_REG_BUCK2DVS1	= 0x22,
-	MAX8997_REG_BUCK2DVS2	= 0x23,
-	MAX8997_REG_BUCK2DVS3	= 0x24,
-	MAX8997_REG_BUCK2DVS4	= 0x25,
-	MAX8997_REG_BUCK2DVS5	= 0x26,
-	MAX8997_REG_BUCK2DVS6	= 0x27,
-	MAX8997_REG_BUCK2DVS7	= 0x28,
-	MAX8997_REG_BUCK2DVS8	= 0x29,
-	MAX8997_REG_BUCK3CTRL	= 0x2a,
-	MAX8997_REG_BUCK3DVS	= 0x2b,
-	MAX8997_REG_BUCK4CTRL	= 0x2c,
-	MAX8997_REG_BUCK4DVS	= 0x2d,
-	MAX8997_REG_BUCK5CTRL	= 0x2e,
-	MAX8997_REG_BUCK5DVS1	= 0x2f,
-	MAX8997_REG_BUCK5DVS2	= 0x30,
-	MAX8997_REG_BUCK5DVS3	= 0x31,
-	MAX8997_REG_BUCK5DVS4	= 0x32,
-	MAX8997_REG_BUCK5DVS5	= 0x33,
-	MAX8997_REG_BUCK5DVS6	= 0x34,
-	MAX8997_REG_BUCK5DVS7	= 0x35,
-	MAX8997_REG_BUCK5DVS8	= 0x36,
-	MAX8997_REG_BUCK6CTRL	= 0x37,
-	MAX8997_REG_BUCK6BPSKIPCTRL	= 0x38,
-	MAX8997_REG_BUCK7CTRL	= 0x39,
-	MAX8997_REG_BUCK7DVS	= 0x3a,
-	MAX8997_REG_LDO1CTRL	= 0x3b,
-	MAX8997_REG_LDO2CTRL	= 0x3c,
-	MAX8997_REG_LDO3CTRL	= 0x3d,
-	MAX8997_REG_LDO4CTRL	= 0x3e,
-	MAX8997_REG_LDO5CTRL	= 0x3f,
-	MAX8997_REG_LDO6CTRL	= 0x40,
-	MAX8997_REG_LDO7CTRL	= 0x41,
-	MAX8997_REG_LDO8CTRL	= 0x42,
-	MAX8997_REG_LDO9CTRL	= 0x43,
-	MAX8997_REG_LDO10CTRL	= 0x44,
-	MAX8997_REG_LDO11CTRL	= 0x45,
-	MAX8997_REG_LDO12CTRL	= 0x46,
-	MAX8997_REG_LDO13CTRL	= 0x47,
-	MAX8997_REG_LDO14CTRL	= 0x48,
-	MAX8997_REG_LDO15CTRL	= 0x49,
-	MAX8997_REG_LDO16CTRL	= 0x4a,
-	MAX8997_REG_LDO17CTRL	= 0x4b,
-	MAX8997_REG_LDO18CTRL	= 0x4c,
-	MAX8997_REG_LDO21CTRL	= 0x4d,
-
-	MAX8997_REG_MBCCTRL1	= 0x50,
-	MAX8997_REG_MBCCTRL2	= 0x51,
-	MAX8997_REG_MBCCTRL3	= 0x52,
-	MAX8997_REG_MBCCTRL4	= 0x53,
-	MAX8997_REG_MBCCTRL5	= 0x54,
-	MAX8997_REG_MBCCTRL6	= 0x55,
-	MAX8997_REG_OTPCGHCVS	= 0x56,
-
-	MAX8997_REG_SAFEOUTCTRL	= 0x5a,
-
-	MAX8997_REG_LBCNFG1	= 0x5e,
-	MAX8997_REG_LBCNFG2	= 0x5f,
-	MAX8997_REG_BBCCTRL	= 0x60,
-
-	MAX8997_REG_FLASH1_CUR	= 0x63, /* 0x63 ~ 0x6e for FLASH */
-	MAX8997_REG_FLASH2_CUR	= 0x64,
-	MAX8997_REG_MOVIE_CUR	= 0x65,
-	MAX8997_REG_GSMB_CUR	= 0x66,
-	MAX8997_REG_BOOST_CNTL	= 0x67,
-	MAX8997_REG_LEN_CNTL	= 0x68,
-	MAX8997_REG_FLASH_CNTL	= 0x69,
-	MAX8997_REG_WDT_CNTL	= 0x6a,
-	MAX8997_REG_MAXFLASH1	= 0x6b,
-	MAX8997_REG_MAXFLASH2	= 0x6c,
-	MAX8997_REG_FLASHSTATUS	= 0x6d,
-	MAX8997_REG_FLASHSTATUSMASK	= 0x6e,
-
-	MAX8997_REG_GPIOCNTL1	= 0x70,
-	MAX8997_REG_GPIOCNTL2	= 0x71,
-	MAX8997_REG_GPIOCNTL3	= 0x72,
-	MAX8997_REG_GPIOCNTL4	= 0x73,
-	MAX8997_REG_GPIOCNTL5	= 0x74,
-	MAX8997_REG_GPIOCNTL6	= 0x75,
-	MAX8997_REG_GPIOCNTL7	= 0x76,
-	MAX8997_REG_GPIOCNTL8	= 0x77,
-	MAX8997_REG_GPIOCNTL9	= 0x78,
-	MAX8997_REG_GPIOCNTL10	= 0x79,
-	MAX8997_REG_GPIOCNTL11	= 0x7a,
-	MAX8997_REG_GPIOCNTL12	= 0x7b,
-
-	MAX8997_REG_LDO1CONFIG	= 0x80,
-	MAX8997_REG_LDO2CONFIG	= 0x81,
-	MAX8997_REG_LDO3CONFIG	= 0x82,
-	MAX8997_REG_LDO4CONFIG	= 0x83,
-	MAX8997_REG_LDO5CONFIG	= 0x84,
-	MAX8997_REG_LDO6CONFIG	= 0x85,
-	MAX8997_REG_LDO7CONFIG	= 0x86,
-	MAX8997_REG_LDO8CONFIG	= 0x87,
-	MAX8997_REG_LDO9CONFIG	= 0x88,
-	MAX8997_REG_LDO10CONFIG	= 0x89,
-	MAX8997_REG_LDO11CONFIG	= 0x8a,
-	MAX8997_REG_LDO12CONFIG	= 0x8b,
-	MAX8997_REG_LDO13CONFIG	= 0x8c,
-	MAX8997_REG_LDO14CONFIG	= 0x8d,
-	MAX8997_REG_LDO15CONFIG	= 0x8e,
-	MAX8997_REG_LDO16CONFIG	= 0x8f,
-	MAX8997_REG_LDO17CONFIG	= 0x90,
-	MAX8997_REG_LDO18CONFIG	= 0x91,
-	MAX8997_REG_LDO21CONFIG	= 0x92,
-
-	MAX8997_REG_DVSOKTIMER1	= 0x97,
-	MAX8997_REG_DVSOKTIMER2	= 0x98,
-	MAX8997_REG_DVSOKTIMER4	= 0x99,
-	MAX8997_REG_DVSOKTIMER5	= 0x9a,
-
-	MAX8997_REG_PMIC_END	= 0x9b,
+	MAX8997_REG_ID,
+	MAX8997_REG_VER,
+	MAX8997_REG_IRQ_SOURCE,
+	MAX8997_REG_IRQ1,
+	MAX8997_REG_IRQ2,
+	MAX8997_REG_IRQ3,
+	MAX8997_REG_IRQ4,
+	MAX8997_REG_RESERVED_0x07,
+	MAX8997_REG_IRQM1,
+	MAX8997_REG_IRQM2,
+	MAX8997_REG_IRQM3,
+	MAX8997_REG_IRQM4,
+	MAX8997_REG_RESERVED_0x0C,
+	MAX8997_REG_STATUS1,
+	MAX8997_REG_STATUS2,
+	MAX8997_REG_STATUS3,
+	MAX8997_REG_STATUS4,
+	MAX8997_REG_RESERVED_0x11,
+	MAX8997_REG_RESERVED_0x12,
+	MAX8997_REG_CONTROL1,
+	MAX8997_REG_CONTROL2,
+	MAX8997_REG_BUCKRAMP,
+	MAX8997_REG_RESERVED_0x16,
+	MAX8997_REG_RESERVED_0x17,
+	MAX8997_REG_BUCK1CTRL,
+	MAX8997_REG_BUCK1DVSTV1,
+	MAX8997_REG_BUCK1DVSTV2,
+	MAX8997_REG_BUCK1DVSTV3,
+	MAX8997_REG_BUCK1DVSTV4,
+	MAX8997_REG_BUCK1DVSTV5,
+	MAX8997_REG_BUCK1DVSTV6,
+	MAX8997_REG_BUCK1DVSTV7,
+	MAX8997_REG_BUCK1DVSTV8,
+	MAX8997_REG_BUCK2CTRL,
+	MAX8997_REG_BUCK2DVSTV1,
+	MAX8997_REG_BUCK2DVSTV2,
+	MAX8997_REG_BUCK2DVSTV3,
+	MAX8997_REG_BUCK2DVSTV4,
+	MAX8997_REG_BUCK2DVSTV5,
+	MAX8997_REG_BUCK2DVSTV6,
+	MAX8997_REG_BUCK2DVSTV7,
+	MAX8997_REG_BUCK2DVSTV8,
+	MAX8997_REG_BUCK3CTRL,
+	MAX8997_REG_BUCK3DVSTV,
+	MAX8997_REG_BUCK4CTRL,
+	MAX8997_REG_BUCK4DVSTV,
+	MAX8997_REG_BUCK5CTRL,
+	MAX8997_REG_BUCK5DVSTV1,
+	MAX8997_REG_BUCK5DVSTV2,
+	MAX8997_REG_BUCK5DVSTV3,
+	MAX8997_REG_BUCK5DVSTV4,
+	MAX8997_REG_BUCK5DVSTV5,
+	MAX8997_REG_BUCK5DVSTV6,
+	MAX8997_REG_BUCK5DVSTV7,
+	MAX8997_REG_BUCK5DVSTV8,
+	MAX8997_REG_BUCK6CTRL1,
+	MAX8997_REG_BUCK6CTRL2,
+	MAX8997_REG_BUCK7CTRL,
+	MAX8997_REG_BUCK7DVSTV,
+	MAX8997_REG_LDO1CTRL,
+	MAX8997_REG_LDO2CTRL,
+	MAX8997_REG_LDO3CTRL,
+	MAX8997_REG_LDO4CTRL,
+	MAX8997_REG_LDO5CTRL,
+	MAX8997_REG_LDO6CTRL,
+	MAX8997_REG_LDO7CTRL,
+	MAX8997_REG_LDO8CTRL,
+	MAX8997_REG_LDO9CTRL,
+	MAX8997_REG_LDO10CTRL,
+	MAX8997_REG_LDO11CTRL,
+	MAX8997_REG_LDO12CTRL,
+	MAX8997_REG_LDO13CTRL,
+	MAX8997_REG_LDO14CTRL,
+	MAX8997_REG_LDO15CTRL,
+	MAX8997_REG_LDO16CTRL,
+	MAX8997_REG_LDO17CTRL,
+	MAX8997_REG_LDO18CTRL,
+	MAX8997_REG_LDO21CTRL,
+	MAX8997_REG_RESERVED_0x4E,
+	MAX8997_REG_RESERVED_0x4F,
+	MAX8997_REG_MBCCTRL1,
+	MAX8997_REG_MBCCTRL2,
+	MAX8997_REG_MBCCTRL3,
+	MAX8997_REG_MBCCTRL4,
+	MAX8997_REG_MBCCTRL5,
+	MAX8997_REG_MBCCTRL6,
+	MAX8997_REG_OTPCGHCVS,
+	MAX8997_REG_RESERVED_0x57,
+	MAX8997_REG_RESERVED_0x58,
+	MAX8997_REG_RESERVED_0x59,
+	MAX8997_REG_SAFEOUTCTRL,
+	MAX8997_REG_RESERVED_0x5B,
+	MAX8997_REG_RESERVED_0x5C,
+	MAX8997_REG_RESERVED_0x5D,
+	MAX8997_REG_LBCNFG1,
+	MAX8997_REG_LBCNFG2,
+	MAX8997_REG_BBCTRL,
+	MAX8997_REG_RESERVED_0x61,
+	MAX8997_REG_RESERVED_0x62,
+	MAX8997_REG_FLASH1_CUR,
+	MAX8997_REG_FLASH2_CUR,
+	MAX8997_REG_MOVIE_CUR,
+	MAX8997_REG_GSMB_CUR,
+	MAX8997_REG_BOOST_CNTL,
+	MAX8997_REG_LED_CNTL,
+	MAX8997_REG_FLASH_CNTL,
+	MAX8997_REG_WDT_CNTL,
+	MAX8997_REG_MAXFLASH1,
+	MAX8997_REG_MAXFLASH2,
+	MAX8997_REG_FLASH_STATUS,
+	MAX8997_REG_FLASH_STATUS_MASK,
+	MAX8997_REG_RESERVED_0x6F,
+	MAX8997_REG_GPIOCNTL1,
+	MAX8997_REG_GPIOCNTL2,
+	MAX8997_REG_GPIOCNTL3,
+	MAX8997_REG_GPIOCNTL4,
+	MAX8997_REG_GPIOCNTL5,
+	MAX8997_REG_GPIOCNTL6,
+	MAX8997_REG_GPIOCNTL7,
+	MAX8997_REG_GPIOCNTL8,
+	MAX8997_REG_GPIOCNTL9,
+	MAX8997_REG_GPIOCNTL10,
+	MAX8997_REG_GPIOCNTL11,
+	MAX8997_REG_GPIOCNTL12,
+	MAX8997_REG_RESERVED_0x7C,
+	MAX8997_REG_RESERVED_0x7D,
+	MAX8997_REG_RESERVED_0x7E,
+	MAX8997_REG_RESERVED_0x7F,
+	MAX8997_REG_LDO1CONFIG,
+	MAX8997_REG_LDO2CONFIG,
+	MAX8997_REG_LDO3CONFIG,
+	MAX8997_REG_LDO4CONFIG,
+	MAX8997_REG_LDO5CONFIG,
+	MAX8997_REG_LDO6CONFIG,
+	MAX8997_REG_LDO7CONFIG,
+	MAX8997_REG_LDO8CONFIG,
+	MAX8997_REG_LDO9CONFIG,
+	MAX8997_REG_LDO10CONFIG,
+	MAX8997_REG_LDO11CONFIG,
+	MAX8997_REG_LDO12CONFIG,
+	MAX8997_REG_LDO13CONFIG,
+	MAX8997_REG_LDO14CONFIG,
+	MAX8997_REG_LDO15CONFIG,
+	MAX8997_REG_LDO16CONFIG,
+	MAX8997_REG_LDO17CONFIG,
+	MAX8997_REG_LDO18CONFIG,
+	MAX8997_REG_LDO21CONFIG,
+	MAX8997_REG_RESERVED_0x93,
+	MAX8997_REG_RESERVED_0x94,
+	MAX8997_REG_RESERVED_0x95,
+	MAX8997_REG_RESERVED_0x96,
+	MAX8997_REG_DVSOKTIMER1,
+	MAX8997_REG_DVSOKTIMER2,
+	MAX8997_REG_DVSOKTIMER4,
+	MAX8997_REG_DVSOKTIMER5,
+
+	MAX8997_REG_PMIC_END
 };
 
+/* MAX8997 MUIC registers */
 enum max8997_muic_reg {
-	MAX8997_MUIC_REG_ID		= 0x0,
-	MAX8997_MUIC_REG_INT1		= 0x1,
-	MAX8997_MUIC_REG_INT2		= 0x2,
-	MAX8997_MUIC_REG_INT3		= 0x3,
-	MAX8997_MUIC_REG_STATUS1	= 0x4,
-	MAX8997_MUIC_REG_STATUS2	= 0x5,
-	MAX8997_MUIC_REG_STATUS3	= 0x6,
-	MAX8997_MUIC_REG_INTMASK1	= 0x7,
-	MAX8997_MUIC_REG_INTMASK2	= 0x8,
-	MAX8997_MUIC_REG_INTMASK3	= 0x9,
-	MAX8997_MUIC_REG_CDETCTRL	= 0xa,
-
-	MAX8997_MUIC_REG_CONTROL1	= 0xc,
-	MAX8997_MUIC_REG_CONTROL2	= 0xd,
-	MAX8997_MUIC_REG_CONTROL3	= 0xe,
-
-	MAX8997_MUIC_REG_END		= 0xf,
+	MAX8997_MUIC_REG_ID = 0,
+	MAX8997_MUIC_REG_INT1,
+	MAX8997_MUIC_REG_INT2,
+	MAX8997_MUIC_REG_INT3,
+	MAX8997_MUIC_REG_STATUS1,
+	MAX8997_MUIC_REG_STATUS2,
+	MAX8997_MUIC_REG_STATUS3,
+	MAX8997_MUIC_REG_INTMASK1,
+	MAX8997_MUIC_REG_INTMASK2,
+	MAX8997_MUIC_REG_INTMASK3,
+	MAX8997_MUIC_REG_CDETCTRL,
+	MAX8997_MUIC_REG_RESERVED_0x0B,
+	MAX8997_MUIC_REG_CTRL1,
+	MAX8997_MUIC_REG_CTRL2,
+	MAX8997_MUIC_REG_CTRL3,
+	MAX8997_MUIC_REG_RESERVED_0x0F,
+
+	MAX8997_MUIC_REG_END
 };
 
 enum max8997_haptic_reg {
-	MAX8997_HAPTIC_REG_GENERAL	= 0x00,
-	MAX8997_HAPTIC_REG_CONF1	= 0x01,
-	MAX8997_HAPTIC_REG_CONF2	= 0x02,
-	MAX8997_HAPTIC_REG_DRVCONF	= 0x03,
-	MAX8997_HAPTIC_REG_CYCLECONF1	= 0x04,
-	MAX8997_HAPTIC_REG_CYCLECONF2	= 0x05,
-	MAX8997_HAPTIC_REG_SIGCONF1	= 0x06,
-	MAX8997_HAPTIC_REG_SIGCONF2	= 0x07,
-	MAX8997_HAPTIC_REG_SIGCONF3	= 0x08,
-	MAX8997_HAPTIC_REG_SIGCONF4	= 0x09,
-	MAX8997_HAPTIC_REG_SIGDC1	= 0x0a,
-	MAX8997_HAPTIC_REG_SIGDC2	= 0x0b,
-	MAX8997_HAPTIC_REG_SIGPWMDC1	= 0x0c,
-	MAX8997_HAPTIC_REG_SIGPWMDC2	= 0x0d,
-	MAX8997_HAPTIC_REG_SIGPWMDC3	= 0x0e,
-	MAX8997_HAPTIC_REG_SIGPWMDC4	= 0x0f,
-	MAX8997_HAPTIC_REG_MTR_REV	= 0x10,
-
-	MAX8997_HAPTIC_REG_END		= 0x11,
+	MAX8997_HAPTIC_REG_GENERAL      = 0x00,
+	MAX8997_HAPTIC_REG_CONF1        = 0x01,
+	MAX8997_HAPTIC_REG_CONF2        = 0x02,
+	MAX8997_HAPTIC_REG_DRVCONF      = 0x03,
+	MAX8997_HAPTIC_REG_CYCLECONF1   = 0x04,
+	MAX8997_HAPTIC_REG_CYCLECONF2   = 0x05,
+	MAX8997_HAPTIC_REG_SIGCONF1     = 0x06,
+	MAX8997_HAPTIC_REG_SIGCONF2     = 0x07,
+	MAX8997_HAPTIC_REG_SIGCONF3     = 0x08,
+	MAX8997_HAPTIC_REG_SIGCONF4     = 0x09,
+	MAX8997_HAPTIC_REG_SIGDC1       = 0x0a,
+	MAX8997_HAPTIC_REG_SIGDC2       = 0x0b,
+	MAX8997_HAPTIC_REG_SIGPWMDC1    = 0x0c,
+	MAX8997_HAPTIC_REG_SIGPWMDC2    = 0x0d,
+	MAX8997_HAPTIC_REG_SIGPWMDC3    = 0x0e,
+	MAX8997_HAPTIC_REG_SIGPWMDC4    = 0x0f,
+	MAX8997_HAPTIC_REG_MTR_REV      = 0x10,
+
+	MAX8997_HAPTIC_REG_END          = 0x11,
 };
 
-/* slave addr = 0x0c: using "2nd part" of rev4 datasheet */
-enum max8997_rtc_reg {
-	MAX8997_RTC_CTRLMASK		= 0x02,
-	MAX8997_RTC_CTRL		= 0x03,
-	MAX8997_RTC_UPDATE1		= 0x04,
-	MAX8997_RTC_UPDATE2		= 0x05,
-	MAX8997_RTC_WTSR_SMPL		= 0x06,
-
-	MAX8997_RTC_SEC			= 0x10,
-	MAX8997_RTC_MIN			= 0x11,
-	MAX8997_RTC_HOUR		= 0x12,
-	MAX8997_RTC_DAY_OF_WEEK		= 0x13,
-	MAX8997_RTC_MONTH		= 0x14,
-	MAX8997_RTC_YEAR		= 0x15,
-	MAX8997_RTC_DAY_OF_MONTH	= 0x16,
-	MAX8997_RTC_ALARM1_SEC		= 0x17,
-	MAX8997_RTC_ALARM1_MIN		= 0x18,
-	MAX8997_RTC_ALARM1_HOUR		= 0x19,
-	MAX8997_RTC_ALARM1_DAY_OF_WEEK	= 0x1a,
-	MAX8997_RTC_ALARM1_MONTH	= 0x1b,
-	MAX8997_RTC_ALARM1_YEAR		= 0x1c,
-	MAX8997_RTC_ALARM1_DAY_OF_MONTH	= 0x1d,
-	MAX8997_RTC_ALARM2_SEC		= 0x1e,
-	MAX8997_RTC_ALARM2_MIN		= 0x1f,
-	MAX8997_RTC_ALARM2_HOUR		= 0x20,
-	MAX8997_RTC_ALARM2_DAY_OF_WEEK	= 0x21,
-	MAX8997_RTC_ALARM2_MONTH	= 0x22,
-	MAX8997_RTC_ALARM2_YEAR		= 0x23,
-	MAX8997_RTC_ALARM2_DAY_OF_MONTH	= 0x24,
+/* IRQ definitions */
+/* The interrupts for board specific purporse are only 18. */
+/* refer arch/arm/mach-s5pv310/include/mach/irqs.h */
+enum {
+	/* PMIC / RTC */
+	/** IRQ1 **/
+	MAX8997_IRQ_PWRONR,
+	MAX8997_IRQ_PWRONF,
+	MAX8997_IRQ_PWRON1SEC,
+	MAX8997_IRQ_JIGONR,
+	MAX8997_IRQ_JIGONF,
+	MAX8997_IRQ_LOWBAT2,
+	MAX8997_IRQ_LOWBAT1,
+	/** IRQ2 **/
+	MAX8997_IRQ_JIGR,
+	MAX8997_IRQ_JIGF,
+	MAX8997_IRQ_MR,
+	MAX8997_IRQ_DVS1OK,
+	MAX8997_IRQ_DVS2OK,
+	MAX8997_IRQ_DVS4OK,
+	MAX8997_IRQ_DVS5OK,
+	/** IRQ3 **/
+	MAX8997_IRQ_CHGINS,
+	MAX8997_IRQ_CHGRM,
+	MAX8997_IRQ_DCINOVP,
+	MAX8997_IRQ_TOPOFF,
+	MAX8997_IRQ_CHGRSTF,
+	MAX8997_IRQ_MBCHGTMEXPD,
+	/** IRQ4 **/
+	MAX8997_IRQ_RTC60S,
+	MAX8997_IRQ_RTCA1,
+	MAX8997_IRQ_RTCA2,
+	MAX8997_IRQ_SMPL_INT,
+	MAX8997_IRQ_RTC1S,
+	MAX8997_IRQ_WTSR,
+	/* MUIC */
+	/** IRQ1 **/
+	MAX8997_IRQ_ADC,
+	MAX8997_IRQ_ADCLOW,
+	MAX8997_IRQ_ADCERR,
+	/** IRQ2 **/
+	MAX8997_IRQ_CHGTYP,
+	MAX8997_IRQ_CHGDETRUN,
+	MAX8997_IRQ_DCDTMR,
+	MAX8997_IRQ_DBCHG,
+	MAX8997_IRQ_VBVOLT,
+	/** IRQ3 **/
+	MAX8997_IRQ_OVP,
+
+	MAX8997_IRQ_NR
 };
 
-enum max8997_irq_source {
-	PMIC_INT1 = 0,
-	PMIC_INT2,
-	PMIC_INT3,
-	PMIC_INT4,
-
-	FUEL_GAUGE, /* Ignored (MAX17042 driver handles) */
-
-	MUIC_INT1,
-	MUIC_INT2,
-	MUIC_INT3,
-
-	GPIO_LOW, /* Not implemented */
-	GPIO_HI, /* Not implemented */
-
-	FLASH_STATUS, /* Not implemented */
-
-	MAX8997_IRQ_GROUP_NR,
+/* MAX8997 various variants */
+enum {
+	TYPE_MAX8997 = 0, /* Default */
 };
 
-enum max8997_irq {
-	MAX8997_PMICIRQ_PWRONR,
-	MAX8997_PMICIRQ_PWRONF,
-	MAX8997_PMICIRQ_PWRON1SEC,
-	MAX8997_PMICIRQ_JIGONR,
-	MAX8997_PMICIRQ_JIGONF,
-	MAX8997_PMICIRQ_LOWBAT2,
-	MAX8997_PMICIRQ_LOWBAT1,
-
-	MAX8997_PMICIRQ_JIGR,
-	MAX8997_PMICIRQ_JIGF,
-	MAX8997_PMICIRQ_MR,
-	MAX8997_PMICIRQ_DVS1OK,
-	MAX8997_PMICIRQ_DVS2OK,
-	MAX8997_PMICIRQ_DVS3OK,
-	MAX8997_PMICIRQ_DVS4OK,
-
-	MAX8997_PMICIRQ_CHGINS,
-	MAX8997_PMICIRQ_CHGRM,
-	MAX8997_PMICIRQ_DCINOVP,
-	MAX8997_PMICIRQ_TOPOFFR,
-	MAX8997_PMICIRQ_CHGRSTF,
-	MAX8997_PMICIRQ_MBCHGTMEXPD,
-
-	MAX8997_PMICIRQ_RTC60S,
-	MAX8997_PMICIRQ_RTCA1,
-	MAX8997_PMICIRQ_RTCA2,
-	MAX8997_PMICIRQ_SMPL_INT,
-	MAX8997_PMICIRQ_RTC1S,
-	MAX8997_PMICIRQ_WTSR,
-
-	MAX8997_MUICIRQ_ADCError,
-	MAX8997_MUICIRQ_ADCLow,
-	MAX8997_MUICIRQ_ADC,
-
-	MAX8997_MUICIRQ_VBVolt,
-	MAX8997_MUICIRQ_DBChg,
-	MAX8997_MUICIRQ_DCDTmr,
-	MAX8997_MUICIRQ_ChgDetRun,
-	MAX8997_MUICIRQ_ChgTyp,
-
-	MAX8997_MUICIRQ_OVP,
-
-	MAX8997_IRQ_NR,
-};
-
-#define MAX8997_NUM_GPIO	12
+/* Interrupt source mask */
+#define MAX8997_INTR_PMIC_MASK		(1 << 1)
+#define MAX8997_INTR_FUELGAUGE_MASK	(1 << 2)
+#define MAX8997_INTR_MUIC_MASK		(1 << 3)
+#define MAX8997_INTR_GPIO_MASK		(1 << 4)
+#define MAX8997_INTR_FLASH_MASK		(1 << 5)
+
+/* PMIC / RTC interrupt mask */
+#define MAX8997_IRQ_PWRONR_MASK		(1 << 0)
+#define MAX8997_IRQ_PWRONF_MASK		(1 << 1)
+#define MAX8997_IRQ_PWRON1SEC_MASK	(1 << 3)
+#define MAX8997_IRQ_JIGONR_MASK		(1 << 4)
+#define MAX8997_IRQ_JIGONF_MASK		(1 << 5)
+#define MAX8997_IRQ_LOWBAT2_MASK	(1 << 6)
+#define MAX8997_IRQ_LOWBAT1_MASK	(1 << 7)
+
+#define MAX8997_IRQ_JIGR_MASK		(1 << 0)
+#define MAX8997_IRQ_JIGF_MASK		(1 << 1)
+#define MAX8997_IRQ_MR_MASK		(1 << 2)
+#define MAX8997_IRQ_DVS1OK_MASK		(1 << 3)
+#define MAX8997_IRQ_DVS2OK_MASK		(1 << 4)
+#define MAX8997_IRQ_DVS4OK_MASK		(1 << 5)
+#define MAX8997_IRQ_DVS5OK_MASK		(1 << 6)
+
+#define MAX8997_IRQ_CHGINS_MASK		(1 << 0)
+#define MAX8997_IRQ_CHGRM_MASK		(1 << 1)
+#define MAX8997_IRQ_DCINOVP_MASK	(1 << 2)
+#define MAX8997_IRQ_TOPOFF_MASK		(1 << 3)
+#define MAX8997_IRQ_CHGRSTF_MASK	(1 << 5)
+#define MAX8997_IRQ_MBCHGTMEXPD_MASK	(1 << 7)
+
+#define MAX8997_IRQ_RTC60S_MASK		(1 << 0)
+#define MAX8997_IRQ_RTCA1_MASK		(1 << 1)
+#define MAX8997_IRQ_RTCA2_MASK		(1 << 2)
+#define MAX8997_IRQ_SMPL_INT_MASK	(1 << 3)
+#define MAX8997_IRQ_RTC1S_MASK		(1 << 4)
+#define MAX8997_IRQ_WTSR_MASK		(1 << 5)
+
+/* MUIC interrupt mask */
+#define MAX8997_IRQ_ADC_MASK		(1 << 0)
+#define MAX8997_IRQ_ADCLOW_MASK		(1 << 1)
+#define MAX8997_IRQ_ADCERR_MASK		(1 << 2)
+
+#define MAX8997_IRQ_CHGTYP_MASK		(1 << 0)
+#define MAX8997_IRQ_CHGDETRUN_MASK	(1 << 1)
+#define MAX8997_IRQ_DCDTMR_MASK		(1 << 2)
+#define MAX8997_IRQ_DBCHG_MASK		(1 << 3)
+#define MAX8997_IRQ_VBVOLT_MASK		(1 << 4)
+
+#define MAX8997_IRQ_OVP_MASK		(1 << 2)
+
+/* RAMP BUCKs register mask */
+#define MAX8997_ENRAMPBUCK1		(1 << 4)
+#define MAX8997_ENRAMPBUCK2		(1 << 5)
+#define MAX8997_ENRAMPBUCK4		(1 << 6)
+#define MAX8997_ENRAMPBUCK5		(1 << 7)
+
+/* Flash LED register mask */
+#define MAX8997_BOOST_EN_MASK		(1 << 6)
+#define MAX8997_BOOST_EN_SHIFT		6
+#define MAX8997_FLASH_EN_MASK		(7 << 0)
+#define MAX8997_FLASH_EN_SHIFT		0
+#define MAX8997_MOVIE_EN_MASK		(7 << 3)
+#define MAX8997_MOVIE_EN_SHIFT		3
+
+/**
+ * struct max8997_dev - max8997 master device for sub-drivers
+ * @dev: master device of the chip (can be used to access platform data)
+ * @i2c: i2c client private data for regulator
+ * @rtc: i2c client private data for rtc
+ * @muic: i2c client private data for muic
+ * @hmotor: i2c client private data for haptic motor
+ * @iolock: mutex for serializing io access
+ * @irqlock: mutex for buslock
+ * @irq_base: base IRQ number for max8997, required for IRQs
+ * @irq: generic IRQ number for max8997
+ * @ono: power onoff IRQ number for max8997
+ * @irq_masks_cur: currently active value
+ * @irq_masks_cache: cached hardware value
+ * @type: indicate which max8997 "variant" is used
+ */
 struct max8997_dev {
 	struct device *dev;
-	struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
-	struct i2c_client *rtc; /* slave addr 0x0c */
-	struct i2c_client *haptic; /* slave addr 0x90 */
-	struct i2c_client *muic; /* slave addr 0x4a */
+	struct i2c_client *i2c;
+	struct i2c_client *rtc;
+	struct i2c_client *muic;
+	struct i2c_client *hmotor;
 	struct mutex iolock;
+	struct mutex irqlock;
 
-	int type;
-	struct platform_device *battery; /* battery control (not fuel gauge) */
-
+	int irq_base;
 	int irq;
 	int ono;
-	int irq_base;
-	bool wakeup;
-	struct mutex irqlock;
-	int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
-	int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
+	u8 irq_masks_cur[MAX8997_NUM_IRQ_REGS];
+	u8 irq_masks_cache[MAX8997_NUM_IRQ_REGS];
+	int type;
+	int wakeup;
 
-	/* For hibernation */
+	/* For hiberantion */
 	u8 reg_dump[MAX8997_REG_PMIC_END + MAX8997_MUIC_REG_END +
 		MAX8997_HAPTIC_REG_END];
-
-	bool gpio_status[MAX8997_NUM_GPIO];
-};
-
-enum max8997_types {
-	TYPE_MAX8997,
-	TYPE_MAX8966,
 };
 
-extern int max8997_irq_init(struct max8997_dev *max8997);
-extern void max8997_irq_exit(struct max8997_dev *max8997);
-extern int max8997_irq_resume(struct max8997_dev *max8997);
+int max8997_irq_init(struct max8997_dev *max8997);
+void max8997_irq_exit(struct max8997_dev *max8997);
 
 extern int max8997_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
 extern int max8997_bulk_read(struct i2c_client *i2c, u8 reg, int count,
-				u8 *buf);
+		u8 *buf);
 extern int max8997_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
 extern int max8997_bulk_write(struct i2c_client *i2c, u8 reg, int count,
-				u8 *buf);
+		u8 *buf);
 extern int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
 
-#define MAX8997_GPIO_INT_BOTH	(0x3 << 4)
-#define MAX8997_GPIO_INT_RISE	(0x2 << 4)
-#define MAX8997_GPIO_INT_FALL	(0x1 << 4)
-
-#define MAX8997_GPIO_INT_MASK	(0x3 << 4)
-#define MAX8997_GPIO_DATA_MASK	(0x1 << 2)
 #endif /*  __LINUX_MFD_MAX8997_PRIV_H */
+
diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
index 60931d0..256ed57 100644
--- a/include/linux/mfd/max8997.h
+++ b/include/linux/mfd/max8997.h
@@ -1,8 +1,9 @@
 /*
- * max8997.h - Driver for the Maxim 8997/8966
+ * max8997.h - Voltage regulator driver for the Maxim 8997
  *
  *  Copyright (C) 2009-2010 Samsung Electrnoics
- *  MyungJoo Ham <myungjoo.ham@samsung.com>
+ *
+ *  based on max8998.h
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,24 +18,20 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- * This driver is based on max8998.h
- *
- * MAX8997 has PMIC, MUIC, HAPTIC, RTC, FLASH, and Fuel Gauge devices.
- * Except Fuel Gauge, every device shares the same I2C bus and included in
- * this mfd driver. Although the fuel gauge is included in the chip, it is
- * excluded from the driver because a) it has a different I2C bus from
- * others and b) it can be enabled simply by using MAX17042 driver.
  */
 
-#ifndef __LINUX_MFD_MAX8998_H
-#define __LINUX_MFD_MAX8998_H
+#ifndef __LINUX_MFD_MAX8997_H
+#define __LINUX_MFD_MAX8997_H
 
-#include <linux/regulator/consumer.h>
+#include <linux/regulator/machine.h>
 
-/* MAX8997/8966 regulator IDs */
-enum max8998_regulators {
-	MAX8997_LDO1 = 0,
+#if defined(CONFIG_MACH_Q1_BD)
+#define MAX8997_SUPPORT_TORCH
+#endif /* CONFIG_MACH_Q1_BD */
+
+/* MAX 8997 regulator ids */
+enum {
+	MAX8997_LDO1 = 1,
 	MAX8997_LDO2,
 	MAX8997_LDO3,
 	MAX8997_LDO4,
@@ -65,53 +62,165 @@ enum max8998_regulators {
 	MAX8997_ENVICHG,
 	MAX8997_ESAFEOUT1,
 	MAX8997_ESAFEOUT2,
-	MAX8997_CHARGER_CV, /* control MBCCV of MBCCTRL3 */
-	MAX8997_CHARGER, /* charger current, MBCCTRL4 */
-	MAX8997_CHARGER_TOPOFF, /* MBCCTRL5 */
+	MAX8997_FLASH_CUR,
+	MAX8997_MOVIE_CUR,
+#ifdef MAX8997_SUPPORT_TORCH
+	MAX8997_FLASH_TORCH,
+#endif /* MAX8997_SUPPORT_TORCH */
 
 	MAX8997_REG_MAX,
 };
 
+/**
+ * max8997_regulator_data - regulator data
+ * @id: regulator id
+ * @initdata: regulator init data (contraints, supplies, ...)
+ */
 struct max8997_regulator_data {
-	int id;
-	struct regulator_init_data *initdata;
+	int				id;
+	struct regulator_init_data	*initdata;
+	int	(*is_valid_regulator)(int, struct regulator_init_data*);
+};
+
+struct max8997_power_data {
+	int		(*set_charger)(int);
+	int		(*topoff_cb) (void);
+	unsigned	batt_detect:1;
+	unsigned	topoff_threshold:2;
+	unsigned	fast_charge:3;	/* charge current */
+};
+
+#ifdef CONFIG_VIBETONZ
+#define MAX8997_MOTOR_REG_CONFIG2		0x2
+#define MOTOR_LRA		(1<<7)
+#define MOTOR_EN		(1<<6)
+#define EXT_PWM		(0<<5)
+#define DIVIDER_128		(1<<1)
+#define DIVIDER_256		(1<<0 | 1<<1)
+
+struct max8997_motor_data {
+	u16 max_timeout;
+	u16 duty;
+	u16 period;
+	u16 reg2;
+	void (*init_hw)(void);
+	void (*motor_en)(bool);
+	unsigned int pwm_id;
+};
+#endif
+
+enum {
+	MAX8997_MUIC_DETACHED = 0,
+	MAX8997_MUIC_ATTACHED
 };
 
+enum {
+	AP_USB_MODE = 0,
+	CP_USB_MODE,
+	AUDIO_MODE,
+};
+
+enum {
+	UART_PATH_CP = 0,
+	UART_PATH_AP,
+};
+
+enum cable_type {
+	CABLE_TYPE_NONE = 0,
+	CABLE_TYPE_USB,
+	CABLE_TYPE_OTG,
+	CABLE_TYPE_TA,
+	CABLE_TYPE_DESKDOCK,
+	CABLE_TYPE_CARDOCK,
+	CABLE_TYPE_STATION,
+	CABLE_TYPE_JIG_UART_OFF,
+	CABLE_TYPE_JIG_UART_OFF_VB,	/* VBUS enabled */
+	CABLE_TYPE_JIG_UART_ON,
+	CABLE_TYPE_JIG_USB_OFF,
+	CABLE_TYPE_JIG_USB_ON,
+	CABLE_TYPE_MHL,
+	CABLE_TYPE_MHL_VB,
+	CABLE_TYPE_UNKNOWN
+};
+
+struct max8997_muic_data {
+	void		(*usb_cb) (u8 attached);
+	void		(*uart_cb) (u8 attached);
+	int		(*charger_cb) (int cable_type);
+	void		(*deskdock_cb) (bool attached);
+	void		(*cardock_cb) (bool attached);
+	void		(*mhl_cb) (int attached);
+	void		(*init_cb) (void);
+	int		(*set_safeout) (int path);
+	bool		(*is_mhl_attached) (void);
+#if !defined(CONFIG_MACH_U1CAMERA_BD)
+	int		(*cfg_uart_gpio) (void);
+#endif /* CONFIG_MACH_U1CAMERA_BD */
+	void		(*jig_uart_cb) (int path);
+	int		(*host_notify_cb) (int enable);
+#if !defined(CONFIG_MACH_U1CAMERA_BD)
+	int		gpio_usb_sel;
+#endif /* CONFIG_MACH_U1CAMERA_BD */
+	int		sw_path;
+#if !defined(CONFIG_MACH_U1CAMERA_BD)
+	int		uart_path;
+#endif /* CONFIG_MACH_U1CAMERA_BD */
+};
+
+struct max8997_buck1_dvs_funcs {
+	int (*set_buck1_dvs_table)(struct max8997_buck1_dvs_funcs *ptr,
+				unsigned int *voltage_table, int arr_size);
+	int (*get_buck1_dvs_table)(struct max8997_buck1_dvs_funcs *ptr,
+				unsigned int *voltage_table);
+};
+
+#define BUCK1_TABLE_SIZE	7
+
+/**
+ * struct max8997_board - packages regulator init data
+ * @regulators: array of defined regulators
+ * @num_regulators: number of regultors used
+ * @irq_base: base IRQ number for max8997, required for IRQs
+ * @ono: power onoff IRQ number for max8997
+ * @wakeup: configure the irq as a wake-up source
+ * @buck1_gpiodvs: enable/disable GPIO DVS for BUCK1
+ * @buck1_voltages: BUCK1 supported voltage list for GPIO DVS(uV)
+ *		it must have descending order.
+ * @buck1_max_vol: maximun voltage for BUCK1 (B1_TV_1)
+ * @buck2_max_vol: maximun voltage for BUCK2 (B2_TV_1)
+ * @buck5_max_vol: maximun voltage for BUCK5 (B5_TV_1)
+ * @buck_set1: BUCK gpio pin 1 to set output voltage
+ * @buck_set2: BUCK gpio pin 2 to set output voltage
+ * @buck_set3: BUCK gpio pin 3 to set output voltage
+ * @buck_ramp_en: enable BUCKx RAMP
+ * @buck_ramp_delay: ramp delay(usec) BUCK RAMP register(0x15)
+ * @flash_cntl_val: value of MAX8997_REG_FLASH_CNTL register
+ * @mr_debounce_time: manual reset debounce time (sec), (default 7sec)
+ */
 struct max8997_platform_data {
-	/* IRQ */
-	int irq_base;
-	int ono;
-	int wakeup;
-
-	/* ---- PMIC ---- */
-	struct max8997_regulator_data *regulators;
-	int num_regulators;
-
-	/*
-	 * SET1~3 DVS GPIOs control Buck1, 2, and 5 simultaneously. Therefore,
-	 * With buckx_gpiodvs enabled, the buckx cannot be controlled
-	 * independently. To control buckx (of 1, 2, and 5) independently,
-	 * disable buckx_gpiodvs and control with BUCKxDVS1 register.
-	 *
-	 * When buckx_gpiodvs and bucky_gpiodvs are both enabled, set_voltage
-	 * on buckx will change the voltage of bucky at the same time.
-	 *
-	 */
-	bool ignore_gpiodvs_side_effect;
-	int buck125_gpios[3]; /* GPIO of [0]SET1, [1]SET2, [2]SET3 */
-	int buck125_default_idx; /* Default value of SET1, 2, 3 */
-	unsigned int buck1_voltage[8]; /* buckx_voltage in uV */
-	bool buck1_gpiodvs;
-	unsigned int buck2_voltage[8];
-	bool buck2_gpiodvs;
-	unsigned int buck5_voltage[8];
-	bool buck5_gpiodvs;
-
-	/* MUIC: Not implemented */
-	/* HAPTIC: Not implemented */
-	/* RTC: Not implemented */
-	/* Flash: Not implemented */
-	/* Charger control: Not implemented */
+	struct max8997_regulator_data	*regulators;
+	int				num_regulators;
+	int				irq_base;
+	int				ono;
+	int				wakeup;
+	bool				buck1_gpiodvs;
+	unsigned int			buck1_max_vol;
+	unsigned int			buck2_max_vol;
+	unsigned int			buck5_max_vol;
+	unsigned int			buck1_voltages[BUCK1_TABLE_SIZE];
+	int				buck_set1;
+	int				buck_set2;
+	int				buck_set3;
+	bool				buck_ramp_en;
+	int				buck_ramp_delay;
+	int				flash_cntl_val;
+	int				mr_debounce_time;
+	struct max8997_power_data	*power;
+	struct max8997_muic_data	*muic;
+#ifdef CONFIG_VIBETONZ
+	struct max8997_motor_data *motor;
+#endif
+	void (*register_buck1_dvs_funcs)(struct max8997_buck1_dvs_funcs *ptr);
 };
 
-#endif /* __LINUX_MFD_MAX8998_H */
+#endif /*  __LINUX_MFD_MAX8997_H */
diff --git a/include/linux/mfd/mc1n2_pdata.h b/include/linux/mfd/mc1n2_pdata.h
new file mode 100644
index 0000000..fe67db4
--- /dev/null
+++ b/include/linux/mfd/mc1n2_pdata.h
@@ -0,0 +1,29 @@
+ /*
+  * Copyright (C) 2008 Samsung Electronics, Inc.
+  *
+  * This software is licensed under the terms of the GNU General Public
+  * License version 2, as published by the Free Software Foundation, and
+  * may be copied, distributed, and modified under those terms.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  */
+
+#ifndef __S5PC210_MC1N2_H
+#define __S5PC210_MC1N2_H
+
+enum mic_type {
+	MAIN_MIC = 0x1,
+	SUB_MIC  = 0x2,
+};
+
+struct mc1n2_platform_data {
+	void (*set_main_mic_bias)(bool on);
+	void (*set_sub_mic_bias)(bool on);
+	int (*set_adc_power_constraints)(int disabled);
+};
+
+#endif
diff --git a/include/linux/mfd/s5m87xx/s5m-core.h b/include/linux/mfd/s5m87xx/s5m-core.h
new file mode 100644
index 0000000..5afc005
--- /dev/null
+++ b/include/linux/mfd/s5m87xx/s5m-core.h
@@ -0,0 +1,385 @@
+/*
+ * s5m-core.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *              http://www.samsung.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_S5M_CORE_H
+#define __LINUX_MFD_S5M_CORE_H
+
+#define NUM_IRQ_REGS	4
+
+enum s5m_device_type {
+	S5M8751X,
+	S5M8763X,
+	S5M8767X,
+};
+
+/* S5M8767 registers */
+enum s5m8767_reg {
+	S5M8767_REG_ID,
+	S5M8767_REG_INT1,
+	S5M8767_REG_INT2,
+	S5M8767_REG_INT3,
+	S5M8767_REG_INT1M,
+	S5M8767_REG_INT2M,
+	S5M8767_REG_INT3M,
+	S5M8767_REG_STATUS1,
+	S5M8767_REG_STATUS2,
+	S5M8767_REG_STATUS3,
+	S5M8767_REG_CTRL1,
+	S5M8767_REG_CTRL2,
+	S5M8767_REG_LOWBAT1,
+	S5M8767_REG_LOWBAT2,
+	S5M8767_REG_BUCHG,
+	S5M8767_REG_DVSRAMP,
+	S5M8767_REG_DVSTIMER2 = 0x10,
+	S5M8767_REG_DVSTIMER3,
+	S5M8767_REG_DVSTIMER4,
+	S5M8767_REG_LDO1,
+	S5M8767_REG_LDO2,
+	S5M8767_REG_LDO3,
+	S5M8767_REG_LDO4,
+	S5M8767_REG_LDO5,
+	S5M8767_REG_LDO6,
+	S5M8767_REG_LDO7,
+	S5M8767_REG_LDO8,
+	S5M8767_REG_LDO9,
+	S5M8767_REG_LDO10,
+	S5M8767_REG_LDO11,
+	S5M8767_REG_LDO12,
+	S5M8767_REG_LDO13,
+	S5M8767_REG_LDO14 = 0x20,
+	S5M8767_REG_LDO15,
+	S5M8767_REG_LDO16,
+	S5M8767_REG_LDO17,
+	S5M8767_REG_LDO18,
+	S5M8767_REG_LDO19,
+	S5M8767_REG_LDO20,
+	S5M8767_REG_LDO21,
+	S5M8767_REG_LDO22,
+	S5M8767_REG_LDO23,
+	S5M8767_REG_LDO24,
+	S5M8767_REG_LDO25,
+	S5M8767_REG_LDO26,
+	S5M8767_REG_LDO27,
+	S5M8767_REG_LDO28,
+	S5M8767_REG_UVLO = 0x31,
+	S5M8767_REG_BUCK1CTRL1,
+	S5M8767_REG_BUCK1CTRL2,
+	S5M8767_REG_BUCK2CTRL,
+	S5M8767_REG_BUCK2DVS1,
+	S5M8767_REG_BUCK2DVS2,
+	S5M8767_REG_BUCK2DVS3,
+	S5M8767_REG_BUCK2DVS4,
+	S5M8767_REG_BUCK2DVS5,
+	S5M8767_REG_BUCK2DVS6,
+	S5M8767_REG_BUCK2DVS7,
+	S5M8767_REG_BUCK2DVS8,
+	S5M8767_REG_BUCK3CTRL,
+	S5M8767_REG_BUCK3DVS1,
+	S5M8767_REG_BUCK3DVS2,
+	S5M8767_REG_BUCK3DVS3,
+	S5M8767_REG_BUCK3DVS4,
+	S5M8767_REG_BUCK3DVS5,
+	S5M8767_REG_BUCK3DVS6,
+	S5M8767_REG_BUCK3DVS7,
+	S5M8767_REG_BUCK3DVS8,
+	S5M8767_REG_BUCK4CTRL,
+	S5M8767_REG_BUCK4DVS1,
+	S5M8767_REG_BUCK4DVS2,
+	S5M8767_REG_BUCK4DVS3,
+	S5M8767_REG_BUCK4DVS4,
+	S5M8767_REG_BUCK4DVS5,
+	S5M8767_REG_BUCK4DVS6,
+	S5M8767_REG_BUCK4DVS7,
+	S5M8767_REG_BUCK4DVS8,
+	S5M8767_REG_BUCK5CTRL1,
+	S5M8767_REG_BUCK5CTRL2,
+	S5M8767_REG_BUCK5CTRL3,
+	S5M8767_REG_BUCK5CTRL4,
+	S5M8767_REG_BUCK5CTRL5,
+	S5M8767_REG_BUCK6CTRL1,
+	S5M8767_REG_BUCK6CTRL2,
+	S5M8767_REG_BUCK7CTRL1,
+	S5M8767_REG_BUCK7CTRL2,
+	S5M8767_REG_BUCK8CTRL1,
+	S5M8767_REG_BUCK8CTRL2,
+	S5M8767_REG_BUCK9CTRL1,
+	S5M8767_REG_BUCK9CTRL2,
+	S5M8767_REG_LDO1CTRL,
+	S5M8767_REG_LDO2_1CTRL,
+	S5M8767_REG_LDO2_2CTRL,
+	S5M8767_REG_LDO2_3CTRL,
+	S5M8767_REG_LDO2_4CTRL,
+	S5M8767_REG_LDO3CTRL,
+	S5M8767_REG_LDO4CTRL,
+	S5M8767_REG_LDO5CTRL,
+	S5M8767_REG_LDO6CTRL,
+	S5M8767_REG_LDO7CTRL,
+	S5M8767_REG_LDO8CTRL,
+	S5M8767_REG_LDO9CTRL,
+	S5M8767_REG_LDO10CTRL,
+	S5M8767_REG_LDO11CTRL,
+	S5M8767_REG_LDO12CTRL,
+	S5M8767_REG_LDO13CTRL,
+	S5M8767_REG_LDO14CTRL,
+	S5M8767_REG_LDO15CTRL,
+	S5M8767_REG_LDO16CTRL,
+	S5M8767_REG_LDO17CTRL,
+	S5M8767_REG_LDO18CTRL,
+	S5M8767_REG_LDO19CTRL,
+	S5M8767_REG_LDO20CTRL,
+	S5M8767_REG_LDO21CTRL,
+	S5M8767_REG_LDO22CTRL,
+	S5M8767_REG_LDO23CTRL,
+	S5M8767_REG_LDO24CTRL,
+	S5M8767_REG_LDO25CTRL,
+	S5M8767_REG_LDO26CTRL,
+	S5M8767_REG_LDO27CTRL,
+	S5M8767_REG_LDO28CTRL,
+};
+
+/* S5M8763 registers */
+enum s5m8763_reg {
+	S5M8763_REG_IRQ1,
+	S5M8763_REG_IRQ2,
+	S5M8763_REG_IRQ3,
+	S5M8763_REG_IRQ4,
+	S5M8763_REG_IRQM1,
+	S5M8763_REG_IRQM2,
+	S5M8763_REG_IRQM3,
+	S5M8763_REG_IRQM4,
+	S5M8763_REG_STATUS1,
+	S5M8763_REG_STATUS2,
+	S5M8763_REG_STATUSM1,
+	S5M8763_REG_STATUSM2,
+	S5M8763_REG_CHGR1,
+	S5M8763_REG_CHGR2,
+	S5M8763_REG_LDO_ACTIVE_DISCHARGE1,
+	S5M8763_REG_LDO_ACTIVE_DISCHARGE2,
+	S5M8763_REG_BUCK_ACTIVE_DISCHARGE3,
+	S5M8763_REG_ONOFF1,
+	S5M8763_REG_ONOFF2,
+	S5M8763_REG_ONOFF3,
+	S5M8763_REG_ONOFF4,
+	S5M8763_REG_BUCK1_VOLTAGE1,
+	S5M8763_REG_BUCK1_VOLTAGE2,
+	S5M8763_REG_BUCK1_VOLTAGE3,
+	S5M8763_REG_BUCK1_VOLTAGE4,
+	S5M8763_REG_BUCK2_VOLTAGE1,
+	S5M8763_REG_BUCK2_VOLTAGE2,
+	S5M8763_REG_BUCK3,
+	S5M8763_REG_BUCK4,
+	S5M8763_REG_LDO1_LDO2,
+	S5M8763_REG_LDO3,
+	S5M8763_REG_LDO4,
+	S5M8763_REG_LDO5,
+	S5M8763_REG_LDO6,
+	S5M8763_REG_LDO7,
+	S5M8763_REG_LDO7_LDO8,
+	S5M8763_REG_LDO9_LDO10,
+	S5M8763_REG_LDO11,
+	S5M8763_REG_LDO12,
+	S5M8763_REG_LDO13,
+	S5M8763_REG_LDO14,
+	S5M8763_REG_LDO15,
+	S5M8763_REG_LDO16,
+	S5M8763_REG_BKCHR,
+	S5M8763_REG_LBCNFG1,
+	S5M8763_REG_LBCNFG2,
+};
+
+enum s5m8767_irq {
+	S5M8767_IRQ_PWRR,
+	S5M8767_IRQ_PWRF,
+	S5M8767_IRQ_PWR1S,
+	S5M8767_IRQ_JIGR,
+	S5M8767_IRQ_JIGF,
+	S5M8767_IRQ_LOWBAT2,
+	S5M8767_IRQ_LOWBAT1,
+
+	S5M8767_IRQ_MRB,
+	S5M8767_IRQ_DVSOK2,
+	S5M8767_IRQ_DVSOK3,
+	S5M8767_IRQ_DVSOK4,
+
+	S5M8767_IRQ_RTC60S,
+	S5M8767_IRQ_RTCA1,
+	S5M8767_IRQ_RTCA2,
+	S5M8767_IRQ_SMPL,
+	S5M8767_IRQ_RTC1S,
+	S5M8767_IRQ_WTSR,
+
+	S5M8767_IRQ_NR,
+};
+
+#define S5M8767_IRQ_PWRR_MASK		(1 << 0)
+#define S5M8767_IRQ_PWRF_MASK		(1 << 1)
+#define S5M8767_IRQ_PWR1S_MASK		(1 << 3)
+#define S5M8767_IRQ_JIGR_MASK		(1 << 4)
+#define S5M8767_IRQ_JIGF_MASK		(1 << 5)
+#define S5M8767_IRQ_LOWBAT2_MASK	(1 << 6)
+#define S5M8767_IRQ_LOWBAT1_MASK	(1 << 7)
+
+#define S5M8767_IRQ_MRB_MASK		(1 << 2)
+#define S5M8767_IRQ_DVSOK2_MASK		(1 << 3)
+#define S5M8767_IRQ_DVSOK3_MASK		(1 << 4)
+#define S5M8767_IRQ_DVSOK4_MASK		(1 << 5)
+
+#define S5M8767_IRQ_RTC60S_MASK		(1 << 0)
+#define S5M8767_IRQ_RTCA1_MASK		(1 << 1)
+#define S5M8767_IRQ_RTCA2_MASK		(1 << 2)
+#define S5M8767_IRQ_SMPL_MASK		(1 << 3)
+#define S5M8767_IRQ_RTC1S_MASK		(1 << 4)
+#define S5M8767_IRQ_WTSR_MASK		(1 << 5)
+
+enum s5m8763_irq {
+	S5M8763_IRQ_DCINF,
+	S5M8763_IRQ_DCINR,
+	S5M8763_IRQ_JIGF,
+	S5M8763_IRQ_JIGR,
+	S5M8763_IRQ_PWRONF,
+	S5M8763_IRQ_PWRONR,
+
+	S5M8763_IRQ_WTSREVNT,
+	S5M8763_IRQ_SMPLEVNT,
+	S5M8763_IRQ_ALARM1,
+	S5M8763_IRQ_ALARM0,
+
+	S5M8763_IRQ_ONKEY1S,
+	S5M8763_IRQ_TOPOFFR,
+	S5M8763_IRQ_DCINOVPR,
+	S5M8763_IRQ_CHGRSTF,
+	S5M8763_IRQ_DONER,
+	S5M8763_IRQ_CHGFAULT,
+
+	S5M8763_IRQ_LOBAT1,
+	S5M8763_IRQ_LOBAT2,
+
+	S5M8763_IRQ_NR,
+};
+
+#define S5M8763_IRQ_DCINF_MASK		(1 << 2)
+#define S5M8763_IRQ_DCINR_MASK		(1 << 3)
+#define S5M8763_IRQ_JIGF_MASK		(1 << 4)
+#define S5M8763_IRQ_JIGR_MASK		(1 << 5)
+#define S5M8763_IRQ_PWRONF_MASK		(1 << 6)
+#define S5M8763_IRQ_PWRONR_MASK		(1 << 7)
+
+#define S5M8763_IRQ_WTSREVNT_MASK	(1 << 0)
+#define S5M8763_IRQ_SMPLEVNT_MASK	(1 << 1)
+#define S5M8763_IRQ_ALARM1_MASK		(1 << 2)
+#define S5M8763_IRQ_ALARM0_MASK		(1 << 3)
+
+#define S5M8763_IRQ_ONKEY1S_MASK	(1 << 0)
+#define S5M8763_IRQ_TOPOFFR_MASK	(1 << 2)
+#define S5M8763_IRQ_DCINOVPR_MASK	(1 << 3)
+#define S5M8763_IRQ_CHGRSTF_MASK	(1 << 4)
+#define S5M8763_IRQ_DONER_MASK		(1 << 5)
+#define S5M8763_IRQ_CHGFAULT_MASK	(1 << 7)
+
+#define S5M8763_IRQ_LOBAT1_MASK		(1 << 0)
+#define S5M8763_IRQ_LOBAT2_MASK		(1 << 1)
+
+#define S5M8763_ENRAMP                  (1 << 4)
+
+/**
+ * struct s5m87xx_dev - s5m87xx master device for sub-drivers
+ * @dev: master device of the chip (can be used to access platform data)
+ * @i2c: i2c client private data for regulator
+ * @rtc: i2c client private data for rtc
+ * @iolock: mutex for serializing io access
+ * @irqlock: mutex for buslock
+ * @irq_base: base IRQ number for s5m87xx, required for IRQs
+ * @irq: generic IRQ number for s5m87xx
+ * @ono: power onoff IRQ number for s5m87xx
+ * @irq_masks_cur: currently active value
+ * @irq_masks_cache: cached hardware value
+ * @type: indicate which s5m87xx "variant" is used
+ */
+struct s5m87xx_dev {
+	struct device *dev;
+	struct i2c_client *i2c;
+	struct i2c_client *rtc;
+	struct mutex iolock;
+	struct mutex irqlock;
+
+	int device_type;
+	int irq_base;
+	int irq;
+	int ono;
+	u8 irq_masks_cur[NUM_IRQ_REGS];
+	u8 irq_masks_cache[NUM_IRQ_REGS];
+	int type;
+	bool wakeup;
+	bool wtsr_smpl;
+};
+
+int s5m_irq_init(struct s5m87xx_dev *s5m87xx);
+void s5m_irq_exit(struct s5m87xx_dev *s5m87xx);
+int s5m_irq_resume(struct s5m87xx_dev *s5m87xx);
+
+extern int s5m_reg_read(struct i2c_client *i2c, u8 reg, u8 *dest);
+extern int s5m_bulk_read(struct i2c_client *i2c, u8 reg, int count, u8 *buf);
+extern int s5m_reg_write(struct i2c_client *i2c, u8 reg, u8 value);
+extern int s5m_bulk_write(struct i2c_client *i2c, u8 reg, int count, u8 *buf);
+extern int s5m_reg_update(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
+
+struct s5m_platform_data {
+	struct s5m_regulator_data	*regulators;
+	struct s5m_opmode_data		*opmode_data;
+
+	int				device_type;
+	int				num_regulators;
+	int				(*cfg_pmic_irq)(void);
+
+	/* IRQ */
+	int				irq_gpio;
+	int				irq_base;
+
+	int				ono;
+	bool				wakeup;
+	bool				buck_voltage_lock;
+
+	int				buck_gpios[3];
+	int				buck_ds[3];
+
+	int				buck2_voltage[8];
+	bool				buck2_gpiodvs;
+	int				buck3_voltage[8];
+	bool				buck3_gpiodvs;
+	int				buck4_voltage[8];
+	bool				buck4_gpiodvs;
+
+	int				buck_set1;
+	int				buck_set2;
+	int				buck_set3;
+	int				buck2_enable;
+	int				buck3_enable;
+	int				buck4_enable;
+	int				buck_default_idx;
+	int				buck2_default_idx;
+	int				buck3_default_idx;
+	int				buck4_default_idx;
+
+	int                             buck_ramp_delay;
+	bool                            buck2_ramp_enable;
+	bool                            buck3_ramp_enable;
+	bool                            buck4_ramp_enable;
+
+	bool				wtsr_smpl;
+
+	int				buck2_init;
+	int				buck3_init;
+	int				buck4_init;
+};
+
+#endif /*  __LINUX_MFD_S5M_CORE_H */
diff --git a/include/linux/mfd/s5m87xx/s5m-pmic.h b/include/linux/mfd/s5m87xx/s5m-pmic.h
new file mode 100644
index 0000000..ba878df
--- /dev/null
+++ b/include/linux/mfd/s5m87xx/s5m-pmic.h
@@ -0,0 +1,115 @@
+/* s5m87xx.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __LINUX_MFD_S5M_PMIC_H
+#define __LINUX_MFD_S5M_PMIC_H
+
+#include <linux/regulator/machine.h>
+
+/* S5M8767 regulator ids */
+enum s5m8767_regulators {
+	S5M8767_LDO1,
+	S5M8767_LDO2,
+	S5M8767_LDO3,
+	S5M8767_LDO4,
+	S5M8767_LDO5,
+	S5M8767_LDO6,
+	S5M8767_LDO7,
+	S5M8767_LDO8,
+	S5M8767_LDO9,
+	S5M8767_LDO10,
+	S5M8767_LDO11,
+	S5M8767_LDO12,
+	S5M8767_LDO13,
+	S5M8767_LDO14,
+	S5M8767_LDO15,
+	S5M8767_LDO16,
+	S5M8767_LDO17,
+	S5M8767_LDO18,
+	S5M8767_LDO19,
+	S5M8767_LDO20,
+	S5M8767_LDO21,
+	S5M8767_LDO22,
+	S5M8767_LDO23,
+	S5M8767_LDO24,
+	S5M8767_LDO25,
+	S5M8767_LDO26,
+	S5M8767_LDO27,
+	S5M8767_LDO28,
+	S5M8767_BUCK1,
+	S5M8767_BUCK2,
+	S5M8767_BUCK3,
+	S5M8767_BUCK4,
+	S5M8767_BUCK5,
+	S5M8767_BUCK6,
+	S5M8767_BUCK7,
+	S5M8767_BUCK8,
+	S5M8767_BUCK9,
+	S5M8767_AP_EN32KHZ,
+	S5M8767_CP_EN32KHZ,
+	S5M8767_BT_EN32KHZ,
+
+	S5M8767_REG_MAX,
+};
+
+
+#define S5M8767_PMIC_EN_SHIFT	6
+
+/* S5M8763 regulator ids */
+enum s5m8763_regulators {
+	S5M8763_LDO1,
+	S5M8763_LDO2,
+	S5M8763_LDO3,
+	S5M8763_LDO4,
+	S5M8763_LDO5,
+	S5M8763_LDO6,
+	S5M8763_LDO7,
+	S5M8763_LDO8,
+	S5M8763_LDO9,
+	S5M8763_LDO10,
+	S5M8763_LDO11,
+	S5M8763_LDO12,
+	S5M8763_LDO13,
+	S5M8763_LDO14,
+	S5M8763_LDO15,
+	S5M8763_LDO16,
+	S5M8763_BUCK1,
+	S5M8763_BUCK2,
+	S5M8763_BUCK3,
+	S5M8763_BUCK4,
+	S5M8763_AP_EN32KHZ,
+	S5M8763_CP_EN32KHZ,
+	S5M8763_ENCHGVI,
+	S5M8763_ESAFEUSB1,
+	S5M8763_ESAFEUSB2,
+};
+
+/**
+ * s5m87xx_regulator_data - regulator data
+ * @id: regulator id
+ * @initdata: regulator init data (contraints, supplies, ...)
+ */
+struct s5m_regulator_data {
+	int				id;
+	struct regulator_init_data	*initdata;
+};
+
+struct s5m_opmode_data {
+	int id;
+	int mode;
+};
+
+enum s5m_opmode {
+	S5M_OPMODE_NORMAL,
+	S5M_OPMODE_LP,
+	S5M_OPMODE_STANDBY,
+};
+
+#endif /*  __LINUX_MFD_S5M_PMIC_H */
diff --git a/include/linux/mfd/s5m87xx/s5m-rtc.h b/include/linux/mfd/s5m87xx/s5m-rtc.h
new file mode 100644
index 0000000..a1caa97
--- /dev/null
+++ b/include/linux/mfd/s5m87xx/s5m-rtc.h
@@ -0,0 +1,95 @@
+/*
+ * s5m-rtc.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *              http://www.samsung.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_S5M_RTC_H
+#define __LINUX_MFD_S5M_RTC_H
+
+enum s5m87xx_rtc_reg {
+	S5M87XX_RTC_SEC,
+	S5M87XX_RTC_MIN,
+	S5M87XX_RTC_HOUR,
+	S5M87XX_RTC_WEEKDAY,
+	S5M87XX_RTC_DATE,
+	S5M87XX_RTC_MONTH,
+	S5M87XX_RTC_YEAR1,
+	S5M87XX_RTC_YEAR2,
+	S5M87XX_ALARM0_SEC,
+	S5M87XX_ALARM0_MIN,
+	S5M87XX_ALARM0_HOUR,
+	S5M87XX_ALARM0_WEEKDAY,
+	S5M87XX_ALARM0_DATE,
+	S5M87XX_ALARM0_MONTH,
+	S5M87XX_ALARM0_YEAR1,
+	S5M87XX_ALARM0_YEAR2,
+	S5M87XX_ALARM1_SEC,
+	S5M87XX_ALARM1_MIN,
+	S5M87XX_ALARM1_HOUR,
+	S5M87XX_ALARM1_WEEKDAY,
+	S5M87XX_ALARM1_DATE,
+	S5M87XX_ALARM1_MONTH,
+	S5M87XX_ALARM1_YEAR1,
+	S5M87XX_ALARM1_YEAR2,
+	S5M87XX_ALARM0_CONF,
+	S5M87XX_ALARM1_CONF,
+	S5M87XX_RTC_STATUS,
+	S5M87XX_WTSR_SMPL_CNTL,
+	S5M87XX_RTC_UDR_CON,
+};
+
+#define RTC_I2C_ADDR		(0x0C >> 1)
+
+#define HOUR_12			(1 << 7)
+#define HOUR_AMPM		(1 << 6)
+#define HOUR_PM			(1 << 5)
+#define ALARM0_STATUS		(1 << 1)
+#define ALARM1_STATUS		(1 << 2)
+#define UPDATE_AD		(1 << 0)
+
+/* RTC Control Register */
+#define BCD_EN_SHIFT		0
+#define BCD_EN_MASK		(1 << BCD_EN_SHIFT)
+#define MODEL24_SHIFT		1
+#define MODEL24_MASK		(1 << MODEL24_SHIFT)
+/* RTC Update Register1 */
+#define RTC_UDR_SHIFT		0
+#define RTC_UDR_MASK		(1 << RTC_UDR_SHIFT)
+#define RTC_TCON_SHIFT		1
+#define RTC_TCON_MASK		(1 << RTC_TCON_SHIFT)
+#define RTC_TIME_EN_SHIFT	3
+#define RTC_TIME_EN_MASK	(1 << RTC_TIME_EN_SHIFT)
+
+/* RTC Hour register */
+#define HOUR_PM_SHIFT		6
+#define HOUR_PM_MASK		(1 << HOUR_PM_SHIFT)
+/* RTC Alarm Enable */
+#define ALARM_ENABLE_SHIFT	7
+#define ALARM_ENABLE_MASK	(1 << ALARM_ENABLE_SHIFT)
+
+#define SMPL_ENABLE_SHIFT	7
+#define SMPL_ENABLE_MASK	(1 << SMPL_ENABLE_SHIFT)
+
+#define WTSR_ENABLE_SHIFT	6
+#define WTSR_ENABLE_MASK	(1 << WTSR_ENABLE_SHIFT)
+
+enum {
+	RTC_SEC = 0,
+	RTC_MIN,
+	RTC_HOUR,
+	RTC_WEEKDAY,
+	RTC_DATE,
+	RTC_MONTH,
+	RTC_YEAR1,
+	RTC_YEAR2,
+};
+
+#endif /*  __LINUX_MFD_S5M_RTC_H */
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index f0b69cd..49d8ab1 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -20,6 +20,7 @@
 enum wm8994_type {
 	WM8994 = 0,
 	WM8958 = 1,
+	WM1811 = 2,
 };
 
 struct regulator_dev;
@@ -55,6 +56,9 @@ struct wm8994 {
 
 	enum wm8994_type type;
 
+	int revision;
+	int cust_id;
+
 	struct device *dev;
 	int (*read_dev)(struct wm8994 *wm8994, unsigned short reg,
 			int bytes, void *dest);
@@ -63,6 +67,8 @@ struct wm8994 {
 
 	void *control_data;
 
+	bool ldo_ena_always_driven;
+
 	int gpio_base;
 	int irq_base;
 
@@ -97,6 +103,8 @@ static inline int wm8994_request_irq(struct wm8994 *wm8994, int irq,
 				     irq_handler_t handler, const char *name,
 				     void *data)
 {
+	if (!wm8994)
+		return -EINVAL;
 	if (!wm8994->irq_base)
 		return -EINVAL;
 	return request_threaded_irq(wm8994->irq_base + irq, NULL, handler,
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index 97cf4f2..630df2d 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -113,6 +113,23 @@ struct wm8958_enh_eq_cfg {
 	u16 regs[WM8958_ENH_EQ_REGS];
 };
 
+/**
+ * Microphone detection rates, used to tune response rates and power
+ * consumption for WM8958/WM1811 microphone detection.
+ *
+ * @sysclk: System clock rate to use this configuration for.
+ * @idle: True if this configuration should use when no accessory is detected,
+ *        false otherwise.
+ * @start: Value for MICD_BIAS_START_TIME register field (not shifted).
+ * @rate: Value for MICD_RATE register field (not shifted).
+ */
+struct wm8958_micd_rate {
+	int sysclk;
+	bool idle;
+	int start;
+	int rate;
+};
+
 struct wm8994_pdata {
 	int gpio_base;
 
@@ -144,6 +161,9 @@ struct wm8994_pdata {
 	int num_enh_eq_cfgs;
 	struct wm8958_enh_eq_cfg *enh_eq_cfgs;
 
+	int num_micd_rates;
+	struct wm8958_micd_rate *micd_rates;
+
         /* LINEOUT can be differential or single ended */
         unsigned int lineout1_diff:1;
         unsigned int lineout2_diff:1;
@@ -165,8 +185,32 @@ struct wm8994_pdata {
         unsigned int jd_scthr:2;
         unsigned int jd_thr:2;
 
+	/* Configure WM1811 jack detection for use with external capacitor */
+	unsigned int jd_ext_cap:1;
+
 	/* WM8958 microphone bias configuration */
 	int micbias[2];
+
+	/* WM8958 microphone detection ranges */
+	u16 micd_lvl_sel;
+
+	/* Disable the internal pull downs on the LDOs if they are
+	 * always driven (eg, connected to an always on supply or
+	 * GPIO that always drives an output.  If they float power
+	 * consumption will rise.
+	 */
+	bool ldo_ena_always_driven;
+
+	/*
+	 * LDO enable delay time
+	 */
+	int ldo_ena_delay;
+
+	/*
+	 * SPKMODE must be pulled internally by the device on this
+	 * system.
+	 */
+	bool spkmode_pu;
 };
 
 #endif
diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h
index f3ee842..0535489 100644
--- a/include/linux/mfd/wm8994/registers.h
+++ b/include/linux/mfd/wm8994/registers.h
@@ -72,6 +72,7 @@
 #define WM8994_DC_SERVO_2                       0x55
 #define WM8994_DC_SERVO_4                       0x57
 #define WM8994_DC_SERVO_READBACK                0x58
+#define WM8994_DC_SERVO_4E			0x59
 #define WM8994_ANALOGUE_HP_1                    0x60
 #define WM8958_MIC_DETECT_1                     0xD0
 #define WM8958_MIC_DETECT_2                     0xD1
@@ -94,11 +95,15 @@
 #define WM8994_FLL1_CONTROL_3                   0x222
 #define WM8994_FLL1_CONTROL_4                   0x223
 #define WM8994_FLL1_CONTROL_5                   0x224
+#define WM8958_FLL1_EFS_1                       0x226
+#define WM8958_FLL1_EFS_2                       0x227
 #define WM8994_FLL2_CONTROL_1                   0x240
 #define WM8994_FLL2_CONTROL_2                   0x241
 #define WM8994_FLL2_CONTROL_3                   0x242
 #define WM8994_FLL2_CONTROL_4                   0x243
 #define WM8994_FLL2_CONTROL_5                   0x244
+#define WM8958_FLL2_EFS_1                       0x246
+#define WM8958_FLL2_EFS_2                       0x247
 #define WM8994_AIF1_CONTROL_1                   0x300
 #define WM8994_AIF1_CONTROL_2                   0x301
 #define WM8994_AIF1_MASTER_SLAVE                0x302
@@ -115,6 +120,7 @@
 #define WM8994_AIF2DAC_LRCLK                    0x315
 #define WM8994_AIF2DAC_DATA                     0x316
 #define WM8994_AIF2ADC_DATA                     0x317
+#define WM1811_AIF2TX_CONTROL                   0x318
 #define WM8958_AIF3_CONTROL_1                   0x320
 #define WM8958_AIF3_CONTROL_2                   0x321
 #define WM8958_AIF3DAC_DATA                     0x322
@@ -133,6 +139,8 @@
 #define WM8994_AIF1_DAC1_FILTERS_2              0x421
 #define WM8994_AIF1_DAC2_FILTERS_1              0x422
 #define WM8994_AIF1_DAC2_FILTERS_2              0x423
+#define WM8958_AIF1_DAC1_NOISE_GATE             0x430
+#define WM8958_AIF1_DAC2_NOISE_GATE             0x431
 #define WM8994_AIF1_DRC1_1                      0x440
 #define WM8994_AIF1_DRC1_2                      0x441
 #define WM8994_AIF1_DRC1_3                      0x442
@@ -163,6 +171,7 @@
 #define WM8994_AIF1_DAC1_EQ_BAND_5_A            0x491
 #define WM8994_AIF1_DAC1_EQ_BAND_5_B            0x492
 #define WM8994_AIF1_DAC1_EQ_BAND_5_PG           0x493
+#define WM8994_AIF1_DAC1_EQ_BAND_1_C            0x494
 #define WM8994_AIF1_DAC2_EQ_GAINS_1             0x4A0
 #define WM8994_AIF1_DAC2_EQ_GAINS_2             0x4A1
 #define WM8994_AIF1_DAC2_EQ_BAND_1_A            0x4A2
@@ -183,6 +192,7 @@
 #define WM8994_AIF1_DAC2_EQ_BAND_5_A            0x4B1
 #define WM8994_AIF1_DAC2_EQ_BAND_5_B            0x4B2
 #define WM8994_AIF1_DAC2_EQ_BAND_5_PG           0x4B3
+#define WM8994_AIF1_DAC2_EQ_BAND_1_C            0x4B4
 #define WM8994_AIF2_ADC_LEFT_VOLUME             0x500
 #define WM8994_AIF2_ADC_RIGHT_VOLUME            0x501
 #define WM8994_AIF2_DAC_LEFT_VOLUME             0x502
@@ -190,6 +200,7 @@
 #define WM8994_AIF2_ADC_FILTERS                 0x510
 #define WM8994_AIF2_DAC_FILTERS_1               0x520
 #define WM8994_AIF2_DAC_FILTERS_2               0x521
+#define WM8958_AIF2_DAC_NOISE_GATE              0x530
 #define WM8994_AIF2_DRC_1                       0x540
 #define WM8994_AIF2_DRC_2                       0x541
 #define WM8994_AIF2_DRC_3                       0x542
@@ -215,6 +226,7 @@
 #define WM8994_AIF2_EQ_BAND_5_A                 0x591
 #define WM8994_AIF2_EQ_BAND_5_B                 0x592
 #define WM8994_AIF2_EQ_BAND_5_PG                0x593
+#define WM8994_AIF2_EQ_BAND_1_C                 0x594
 #define WM8994_DAC1_MIXER_VOLUMES               0x600
 #define WM8994_DAC1_LEFT_MIXER_ROUTING          0x601
 #define WM8994_DAC1_RIGHT_MIXER_ROUTING         0x602
@@ -238,6 +250,7 @@
 #define WM8994_GPIO_4                           0x703
 #define WM8994_GPIO_5                           0x704
 #define WM8994_GPIO_6                           0x705
+#define WM1811_JACKDET_CTRL			0x705
 #define WM8994_GPIO_7                           0x706
 #define WM8994_GPIO_8                           0x707
 #define WM8994_GPIO_9                           0x708
@@ -260,7 +273,43 @@
 #define WM8958_DSP2_RELEASETIME                 0xA03
 #define WM8958_DSP2_VERMAJMIN                   0xA04
 #define WM8958_DSP2_VERBUILD                    0xA05
+#define WM8958_DSP2_TESTREG                     0xA06
+#define WM8958_DSP2_XORREG                      0xA07
+#define WM8958_DSP2_SHIFTMAXX                   0xA08
+#define WM8958_DSP2_SHIFTMAXY                   0xA09
+#define WM8958_DSP2_SHIFTMAXZ                   0xA0A
+#define WM8958_DSP2_SHIFTMAXEXTLO               0xA0B
+#define WM8958_DSP2_AESSELECT                   0xA0C
 #define WM8958_DSP2_EXECCONTROL                 0xA0D
+#define WM8958_DSP2_SAMPLEBREAK                 0xA0E
+#define WM8958_DSP2_COUNTBREAK                  0xA0F
+#define WM8958_DSP2_INTSTATUS                   0xA10
+#define WM8958_DSP2_EVENTSTATUS                 0xA11
+#define WM8958_DSP2_INTMASK                     0xA12
+#define WM8958_DSP2_CONFIGDWIDTH                0xA13
+#define WM8958_DSP2_CONFIGINSTR                 0xA14
+#define WM8958_DSP2_CONFIGDMEM                  0xA15
+#define WM8958_DSP2_CONFIGDELAYS                0xA16
+#define WM8958_DSP2_CONFIGNUMIO                 0xA17
+#define WM8958_DSP2_CONFIGEXTDEPTH              0xA18
+#define WM8958_DSP2_CONFIGMULTIPLIER            0xA19
+#define WM8958_DSP2_CONFIGCTRLDWIDTH            0xA1A
+#define WM8958_DSP2_CONFIGPIPELINE              0xA1B
+#define WM8958_DSP2_SHIFTMAXEXTHI               0xA1C
+#define WM8958_DSP2_SWVERSIONREG                0xA1D
+#define WM8958_DSP2_CONFIGXMEM                  0xA1E
+#define WM8958_DSP2_CONFIGYMEM                  0xA1F
+#define WM8958_DSP2_CONFIGZMEM                  0xA20
+#define WM8958_FW_BUILD_1                       0x2000
+#define WM8958_FW_BUILD_0                       0x2001
+#define WM8958_FW_ID_1                          0x2002
+#define WM8958_FW_ID_0                          0x2003
+#define WM8958_FW_MAJOR_1                       0x2004
+#define WM8958_FW_MAJOR_0                       0x2005
+#define WM8958_FW_MINOR_1                       0x2006
+#define WM8958_FW_MINOR_0                       0x2007
+#define WM8958_FW_PATCH_1                       0x2008
+#define WM8958_FW_PATCH_0                       0x2009
 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1     0x2200
 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2     0x2201
 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1     0x2202
@@ -329,6 +378,14 @@
 #define WM8958_MBC_B2_PG2_2                     0x242D
 #define WM8958_MBC_B1_PG2_1                     0x242E
 #define WM8958_MBC_B1_PG2_2                     0x242F
+#define WM8958_MBC_CROSSOVER_1                  0x2600
+#define WM8958_MBC_CROSSOVER_2                  0x2601
+#define WM8958_MBC_HPF_1                        0x2602
+#define WM8958_MBC_HPF_2                        0x2603
+#define WM8958_MBC_LPF_1                        0x2606
+#define WM8958_MBC_LPF_2                        0x2607
+#define WM8958_MBC_RMS_LIMIT_1                  0x260A
+#define WM8958_MBC_RMS_LIMIT_2                  0x260B
 #define WM8994_WRITE_SEQUENCER_0                0x3000
 #define WM8994_WRITE_SEQUENCER_1                0x3001
 #define WM8994_WRITE_SEQUENCER_2                0x3002
@@ -1848,6 +1905,9 @@
 /*
  * R57 (0x39) - AntiPOP (2)
  */
+#define WM1811_JACKDET_MODE_MASK                0x0180  /* JACKDET_MODE - [8:7] */
+#define WM1811_JACKDET_MODE_SHIFT                    7  /* JACKDET_MODE - [8:7] */
+#define WM1811_JACKDET_MODE_WIDTH                    2  /* JACKDET_MODE - [8:7] */
 #define WM8994_MICB2_DISCH                      0x0100  /* MICB2_DISCH */
 #define WM8994_MICB2_DISCH_MASK                 0x0100  /* MICB2_DISCH */
 #define WM8994_MICB2_DISCH_SHIFT                     8  /* MICB2_DISCH */
@@ -1921,6 +1981,59 @@
 #define WM8994_LDO2_DISCH_WIDTH                      1  /* LDO2_DISCH */
 
 /*
+ * R61 (0x3D) - MICBIAS1
+ */
+#define WM8958_MICB1_RATE                       0x0020  /* MICB1_RATE */
+#define WM8958_MICB1_RATE_MASK                  0x0020  /* MICB1_RATE */
+#define WM8958_MICB1_RATE_SHIFT                      5  /* MICB1_RATE */
+#define WM8958_MICB1_RATE_WIDTH                      1  /* MICB1_RATE */
+#define WM8958_MICB1_MODE                       0x0010  /* MICB1_MODE */
+#define WM8958_MICB1_MODE_MASK                  0x0010  /* MICB1_MODE */
+#define WM8958_MICB1_MODE_SHIFT                      4  /* MICB1_MODE */
+#define WM8958_MICB1_MODE_WIDTH                      1  /* MICB1_MODE */
+#define WM8958_MICB1_LVL_MASK                   0x000E  /* MICB1_LVL - [3:1] */
+#define WM8958_MICB1_LVL_SHIFT                       1  /* MICB1_LVL - [3:1] */
+#define WM8958_MICB1_LVL_WIDTH                       3  /* MICB1_LVL - [3:1] */
+#define WM8958_MICB1_DISCH                      0x0001  /* MICB1_DISCH */
+#define WM8958_MICB1_DISCH_MASK                 0x0001  /* MICB1_DISCH */
+#define WM8958_MICB1_DISCH_SHIFT                     0  /* MICB1_DISCH */
+#define WM8958_MICB1_DISCH_WIDTH                     1  /* MICB1_DISCH */
+
+/*
+ * R62 (0x3E) - MICBIAS2
+ */
+#define WM8958_MICB2_RATE                       0x0020  /* MICB2_RATE */
+#define WM8958_MICB2_RATE_MASK                  0x0020  /* MICB2_RATE */
+#define WM8958_MICB2_RATE_SHIFT                      5  /* MICB2_RATE */
+#define WM8958_MICB2_RATE_WIDTH                      1  /* MICB2_RATE */
+#define WM8958_MICB2_MODE                       0x0010  /* MICB2_MODE */
+#define WM8958_MICB2_MODE_MASK                  0x0010  /* MICB2_MODE */
+#define WM8958_MICB2_MODE_SHIFT                      4  /* MICB2_MODE */
+#define WM8958_MICB2_MODE_WIDTH                      1  /* MICB2_MODE */
+#define WM8958_MICB2_LVL_MASK                   0x000E  /* MICB2_LVL - [3:1] */
+#define WM8958_MICB2_LVL_SHIFT                       1  /* MICB2_LVL - [3:1] */
+#define WM8958_MICB2_LVL_WIDTH                       3  /* MICB2_LVL - [3:1] */
+#define WM8958_MICB2_DISCH                      0x0001  /* MICB2_DISCH */
+#define WM8958_MICB2_DISCH_MASK                 0x0001  /* MICB2_DISCH */
+#define WM8958_MICB2_DISCH_SHIFT                     0  /* MICB2_DISCH */
+#define WM8958_MICB2_DISCH_WIDTH                     1  /* MICB2_DISCH */
+
+/*
+ * R210 (0xD2) - Mic Detect 3
+ */
+#define WM8958_MICD_LVL_MASK                    0x07FC  /* MICD_LVL - [10:2] */
+#define WM8958_MICD_LVL_SHIFT                        2  /* MICD_LVL - [10:2] */
+#define WM8958_MICD_LVL_WIDTH                        9  /* MICD_LVL - [10:2] */
+#define WM8958_MICD_VALID                       0x0002  /* MICD_VALID */
+#define WM8958_MICD_VALID_MASK                  0x0002  /* MICD_VALID */
+#define WM8958_MICD_VALID_SHIFT                      1  /* MICD_VALID */
+#define WM8958_MICD_VALID_WIDTH                      1  /* MICD_VALID */
+#define WM8958_MICD_STS                         0x0001  /* MICD_STS */
+#define WM8958_MICD_STS_MASK                    0x0001  /* MICD_STS */
+#define WM8958_MICD_STS_SHIFT                        0  /* MICD_STS */
+#define WM8958_MICD_STS_WIDTH                        1  /* MICD_STS */
+
+/*
  * R76 (0x4C) - Charge Pump (1)
  */
 #define WM8994_CP_ENA                           0x8000  /* CP_ENA */
@@ -2027,6 +2140,10 @@
 /*
  * R96 (0x60) - Analogue HP (1)
  */
+#define WM1811_HPOUT1_ATTN                      0x0100  /* HPOUT1_ATTN */
+#define WM1811_HPOUT1_ATTN_MASK                 0x0100  /* HPOUT1_ATTN */
+#define WM1811_HPOUT1_ATTN_SHIFT                     8  /* HPOUT1_ATTN */
+#define WM1811_HPOUT1_ATTN_WIDTH                     1  /* HPOUT1_ATTN */
 #define WM8994_HPOUT1L_RMV_SHORT                0x0080  /* HPOUT1L_RMV_SHORT */
 #define WM8994_HPOUT1L_RMV_SHORT_MASK           0x0080  /* HPOUT1L_RMV_SHORT */
 #define WM8994_HPOUT1L_RMV_SHORT_SHIFT               7  /* HPOUT1L_RMV_SHORT */
@@ -2095,6 +2212,9 @@
 /*
  * R256 (0x100) - Chip Revision
  */
+#define WM8994_CUST_ID_MASK                     0xFF00  /* CUST_ID - [15:8] */
+#define WM8994_CUST_ID_SHIFT                         8  /* CUST_ID - [15:8] */
+#define WM8994_CUST_ID_WIDTH                         8  /* CUST_ID - [15:8] */
 #define WM8994_CHIP_REV_MASK                    0x000F  /* CHIP_REV - [3:0] */
 #define WM8994_CHIP_REV_SHIFT                        0  /* CHIP_REV - [3:0] */
 #define WM8994_CHIP_REV_WIDTH                        4  /* CHIP_REV - [3:0] */
@@ -2328,6 +2448,10 @@
 /*
  * R548 (0x224) - FLL1 Control (5)
  */
+#define WM8958_FLL1_BYP                         0x8000  /* FLL1_BYP */
+#define WM8958_FLL1_BYP_MASK                    0x8000  /* FLL1_BYP */
+#define WM8958_FLL1_BYP_SHIFT                       15  /* FLL1_BYP */
+#define WM8958_FLL1_BYP_WIDTH                        1  /* FLL1_BYP */
 #define WM8994_FLL1_FRC_NCO_VAL_MASK            0x1F80  /* FLL1_FRC_NCO_VAL - [12:7] */
 #define WM8994_FLL1_FRC_NCO_VAL_SHIFT                7  /* FLL1_FRC_NCO_VAL - [12:7] */
 #define WM8994_FLL1_FRC_NCO_VAL_WIDTH                6  /* FLL1_FRC_NCO_VAL - [12:7] */
@@ -2343,6 +2467,24 @@
 #define WM8994_FLL1_REFCLK_SRC_WIDTH                 2  /* FLL1_REFCLK_SRC - [1:0] */
 
 /*
+ * R550 (0x226) - FLL1 EFS 1
+ */
+#define WM8958_FLL1_LAMBDA_MASK                 0xFFFF  /* FLL1_LAMBDA - [15:0] */
+#define WM8958_FLL1_LAMBDA_SHIFT                     0  /* FLL1_LAMBDA - [15:0] */
+#define WM8958_FLL1_LAMBDA_WIDTH                    16  /* FLL1_LAMBDA - [15:0] */
+
+/*
+ * R551 (0x227) - FLL1 EFS 2
+ */
+#define WM8958_FLL1_LFSR_SEL_MASK               0x0006  /* FLL1_LFSR_SEL - [2:1] */
+#define WM8958_FLL1_LFSR_SEL_SHIFT                   1  /* FLL1_LFSR_SEL - [2:1] */
+#define WM8958_FLL1_LFSR_SEL_WIDTH                   2  /* FLL1_LFSR_SEL - [2:1] */
+#define WM8958_FLL1_EFS_ENA                     0x0001  /* FLL1_EFS_ENA */
+#define WM8958_FLL1_EFS_ENA_MASK                0x0001  /* FLL1_EFS_ENA */
+#define WM8958_FLL1_EFS_ENA_SHIFT                    0  /* FLL1_EFS_ENA */
+#define WM8958_FLL1_EFS_ENA_WIDTH                    1  /* FLL1_EFS_ENA */
+
+/*
  * R576 (0x240) - FLL2 Control (1)
  */
 #define WM8994_FLL2_FRAC                        0x0004  /* FLL2_FRAC */
@@ -2391,6 +2533,10 @@
 /*
  * R580 (0x244) - FLL2 Control (5)
  */
+#define WM8958_FLL2_BYP                         0x8000  /* FLL2_BYP */
+#define WM8958_FLL2_BYP_MASK                    0x8000  /* FLL2_BYP */
+#define WM8958_FLL2_BYP_SHIFT                       15  /* FLL2_BYP */
+#define WM8958_FLL2_BYP_WIDTH                        1  /* FLL2_BYP */
 #define WM8994_FLL2_FRC_NCO_VAL_MASK            0x1F80  /* FLL2_FRC_NCO_VAL - [12:7] */
 #define WM8994_FLL2_FRC_NCO_VAL_SHIFT                7  /* FLL2_FRC_NCO_VAL - [12:7] */
 #define WM8994_FLL2_FRC_NCO_VAL_WIDTH                6  /* FLL2_FRC_NCO_VAL - [12:7] */
@@ -2406,6 +2552,24 @@
 #define WM8994_FLL2_REFCLK_SRC_WIDTH                 2  /* FLL2_REFCLK_SRC - [1:0] */
 
 /*
+ * R582 (0x246) - FLL2 EFS 1
+ */
+#define WM8958_FLL2_LAMBDA_MASK                 0xFFFF  /* FLL2_LAMBDA - [15:0] */
+#define WM8958_FLL2_LAMBDA_SHIFT                     0  /* FLL2_LAMBDA - [15:0] */
+#define WM8958_FLL2_LAMBDA_WIDTH                    16  /* FLL2_LAMBDA - [15:0] */
+
+/*
+ * R583 (0x247) - FLL2 EFS 2
+ */
+#define WM8958_FLL2_LFSR_SEL_MASK               0x0006  /* FLL2_LFSR_SEL - [2:1] */
+#define WM8958_FLL2_LFSR_SEL_SHIFT                   1  /* FLL2_LFSR_SEL - [2:1] */
+#define WM8958_FLL2_LFSR_SEL_WIDTH                   2  /* FLL2_LFSR_SEL - [2:1] */
+#define WM8958_FLL2_EFS_ENA                     0x0001  /* FLL2_EFS_ENA */
+#define WM8958_FLL2_EFS_ENA_MASK                0x0001  /* FLL2_EFS_ENA */
+#define WM8958_FLL2_EFS_ENA_SHIFT                    0  /* FLL2_EFS_ENA */
+#define WM8958_FLL2_EFS_ENA_WIDTH                    1  /* FLL2_EFS_ENA */
+
+/*
  * R768 (0x300) - AIF1 Control (1)
  */
 #define WM8994_AIF1ADCL_SRC                     0x8000  /* AIF1ADCL_SRC */
@@ -2949,6 +3113,34 @@
 #define WM8994_AIF1DAC2_3D_ENA_WIDTH                 1  /* AIF1DAC2_3D_ENA */
 
 /*
+ * R1072 (0x430) - AIF1 DAC1 Noise Gate
+ */
+#define WM8958_AIF1DAC1_NG_HLD_MASK             0x0060  /* AIF1DAC1_NG_HLD - [6:5] */
+#define WM8958_AIF1DAC1_NG_HLD_SHIFT                 5  /* AIF1DAC1_NG_HLD - [6:5] */
+#define WM8958_AIF1DAC1_NG_HLD_WIDTH                 2  /* AIF1DAC1_NG_HLD - [6:5] */
+#define WM8958_AIF1DAC1_NG_THR_MASK             0x000E  /* AIF1DAC1_NG_THR - [3:1] */
+#define WM8958_AIF1DAC1_NG_THR_SHIFT                 1  /* AIF1DAC1_NG_THR - [3:1] */
+#define WM8958_AIF1DAC1_NG_THR_WIDTH                 3  /* AIF1DAC1_NG_THR - [3:1] */
+#define WM8958_AIF1DAC1_NG_ENA                  0x0001  /* AIF1DAC1_NG_ENA */
+#define WM8958_AIF1DAC1_NG_ENA_MASK             0x0001  /* AIF1DAC1_NG_ENA */
+#define WM8958_AIF1DAC1_NG_ENA_SHIFT                 0  /* AIF1DAC1_NG_ENA */
+#define WM8958_AIF1DAC1_NG_ENA_WIDTH                 1  /* AIF1DAC1_NG_ENA */
+
+/*
+ * R1073 (0x431) - AIF1 DAC2 Noise Gate
+ */
+#define WM8958_AIF1DAC2_NG_HLD_MASK             0x0060  /* AIF1DAC2_NG_HLD - [6:5] */
+#define WM8958_AIF1DAC2_NG_HLD_SHIFT                 5  /* AIF1DAC2_NG_HLD - [6:5] */
+#define WM8958_AIF1DAC2_NG_HLD_WIDTH                 2  /* AIF1DAC2_NG_HLD - [6:5] */
+#define WM8958_AIF1DAC2_NG_THR_MASK             0x000E  /* AIF1DAC2_NG_THR - [3:1] */
+#define WM8958_AIF1DAC2_NG_THR_SHIFT                 1  /* AIF1DAC2_NG_THR - [3:1] */
+#define WM8958_AIF1DAC2_NG_THR_WIDTH                 3  /* AIF1DAC2_NG_THR - [3:1] */
+#define WM8958_AIF1DAC2_NG_ENA                  0x0001  /* AIF1DAC2_NG_ENA */
+#define WM8958_AIF1DAC2_NG_ENA_MASK             0x0001  /* AIF1DAC2_NG_ENA */
+#define WM8958_AIF1DAC2_NG_ENA_SHIFT                 0  /* AIF1DAC2_NG_ENA */
+#define WM8958_AIF1DAC2_NG_ENA_WIDTH                 1  /* AIF1DAC2_NG_ENA */
+
+/*
  * R1088 (0x440) - AIF1 DRC1 (1)
  */
 #define WM8994_AIF1DRC1_SIG_DET_RMS_MASK        0xF800  /* AIF1DRC1_SIG_DET_RMS - [15:11] */
@@ -3560,6 +3752,20 @@
 #define WM8994_AIF2DAC_3D_ENA_WIDTH                  1  /* AIF2DAC_3D_ENA */
 
 /*
+ * R1328 (0x530) - AIF2 DAC Noise Gate
+ */
+#define WM8958_AIF2DAC_NG_HLD_MASK              0x0060  /* AIF2DAC_NG_HLD - [6:5] */
+#define WM8958_AIF2DAC_NG_HLD_SHIFT                  5  /* AIF2DAC_NG_HLD - [6:5] */
+#define WM8958_AIF2DAC_NG_HLD_WIDTH                  2  /* AIF2DAC_NG_HLD - [6:5] */
+#define WM8958_AIF2DAC_NG_THR_MASK              0x000E  /* AIF2DAC_NG_THR - [3:1] */
+#define WM8958_AIF2DAC_NG_THR_SHIFT                  1  /* AIF2DAC_NG_THR - [3:1] */
+#define WM8958_AIF2DAC_NG_THR_WIDTH                  3  /* AIF2DAC_NG_THR - [3:1] */
+#define WM8958_AIF2DAC_NG_ENA                   0x0001  /* AIF2DAC_NG_ENA */
+#define WM8958_AIF2DAC_NG_ENA_MASK              0x0001  /* AIF2DAC_NG_ENA */
+#define WM8958_AIF2DAC_NG_ENA_SHIFT                  0  /* AIF2DAC_NG_ENA */
+#define WM8958_AIF2DAC_NG_ENA_WIDTH                  1  /* AIF2DAC_NG_ENA */
+
+/*
  * R1344 (0x540) - AIF2 DRC (1)
  */
 #define WM8994_AIF2DRC_SIG_DET_RMS_MASK         0xF800  /* AIF2DRC_SIG_DET_RMS - [15:11] */
@@ -4084,6 +4290,18 @@
 #define WM8994_STL_SEL_WIDTH                         1  /* STL_SEL */
 
 /*
+ * R1797 (0x705) - JACKDET Ctrl
+ */
+#define WM1811_JACKDET_DB                       0x0100  /* JACKDET_DB */
+#define WM1811_JACKDET_DB_MASK                  0x0100  /* JACKDET_DB */
+#define WM1811_JACKDET_DB_SHIFT                      8  /* JACKDET_DB */
+#define WM1811_JACKDET_DB_WIDTH                      1  /* JACKDET_DB */
+#define WM1811_JACKDET_LVL                      0x0040  /* JACKDET_LVL */
+#define WM1811_JACKDET_LVL_MASK                 0x0040  /* JACKDET_LVL */
+#define WM1811_JACKDET_LVL_SHIFT                     6  /* JACKDET_LVL */
+#define WM1811_JACKDET_LVL_WIDTH                     1  /* JACKDET_LVL */
+
+/*
  * R1824 (0x720) - Pull Control (1)
  */
 #define WM8994_DMICDAT2_PU                      0x0800  /* DMICDAT2_PU */