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author | Michael S. Tsirkin <mst@mellanox.co.il> | 2007-02-10 23:15:08 +0200 |
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committer | Roland Dreier <rolandd@cisco.com> | 2007-02-12 16:16:29 -0800 |
commit | 391e4dea7189eef32b0c2d121e7e047110c1b83c (patch) | |
tree | 99cfb7f912837fb6f37ae290c9f1345d218eab06 /kernel/posix-cpu-timers.c | |
parent | 1d1f19cfce7687b557cebdc41bf8a5eeba8a9882 (diff) | |
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IB/mthca: Fix access to MTT and MPT tables on non-cache-coherent CPUs
We allocate the MTT table with alloc_pages() and then do pci_map_sg(),
so we must call pci_dma_sync_sg() after the CPU writes to the MTT
table. This works since the device will never write MTTs on mem-free
HCAs, once we get rid of the use of the WRITE_MTT firmware command.
This change is needed to make that work, and is an improvement for
now, since it gives FMRs a chance at working.
For MPTs, both the device and CPU might write there, so we must
allocate DMA coherent memory for these.
Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'kernel/posix-cpu-timers.c')
0 files changed, 0 insertions, 0 deletions