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-rw-r--r--arch/arm/mach-ux500/cpu-u8500.c19
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h29
2 files changed, 41 insertions, 7 deletions
diff --git a/arch/arm/mach-ux500/cpu-u8500.c b/arch/arm/mach-ux500/cpu-u8500.c
index 588b059..f368504 100644
--- a/arch/arm/mach-ux500/cpu-u8500.c
+++ b/arch/arm/mach-ux500/cpu-u8500.c
@@ -40,15 +40,27 @@ static struct map_desc u8500_io_desc[] __initdata = {
__IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
__IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K),
__IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
- __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
__IO_DEV_DESC(U8500_TWD_BASE, SZ_4K),
__IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
__IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
};
+static struct map_desc u8500ed_io_desc[] __initdata = {
+ __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K),
+};
+
+static struct map_desc u8500v1_io_desc[] __initdata = {
+ __IO_DEV_DESC(U8500_MTU0_BASE_V1, SZ_4K),
+};
+
void __init u8500_map_io(void)
{
iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
+
+ if (cpu_is_u8500ed())
+ iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc));
+ else
+ iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc));
}
void __init u8500_init_irq(void)
@@ -75,7 +87,10 @@ static void __init u8500_timer_init(void)
twd_base = __io_address(U8500_TWD_BASE);
#endif
/* Setup the MTU base */
- mtu_base = __io_address(U8500_MTU0_BASE);
+ if (cpu_is_u8500ed())
+ mtu_base = __io_address(U8500_MTU0_BASE_ED);
+ else
+ mtu_base = __io_address(U8500_MTU0_BASE_V1);
nmdk_timer_init();
}
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 04ea836..f29a43d 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -56,16 +56,19 @@
#define U8500_TWD_SIZE 0x100
/* per7 base addressess */
-#define U8500_CR_BASE (U8500_PER7_BASE + 0x8000)
-#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000)
-#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000)
-#define U8500_TZPC0_BASE (U8500_PER7_BASE + 0xc000)
-#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
+#define U8500_CR_BASE_ED (U8500_PER7_BASE + 0x8000)
+#define U8500_MTU0_BASE_ED (U8500_PER7_BASE + 0xa000)
+#define U8500_MTU1_BASE_ED (U8500_PER7_BASE + 0xb000)
+#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE + 0xc000)
+#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE + 0xf000)
/* per6 base addressess */
#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
+#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000)
+#define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000)
+#define U8500_CR_BASE_V1 (U8500_PER6_BASE + 0x8000)
#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
@@ -128,4 +131,20 @@
/* ST-Ericsson modified pl022 id */
#define SSP_PER_ID 0x01080022
+#ifndef __ASSEMBLY__
+
+#include <asm/cputype.h>
+
+static inline bool cpu_is_u8500ed(void)
+{
+ return (read_cpuid_id() & 15) == 0;
+}
+
+static inline bool cpu_is_u8500v1(void)
+{
+ return (read_cpuid_id() & 15) == 1;
+}
+
+#endif
+
#endif /* __MACH_HARDWARE_H */