diff options
Diffstat (limited to 'drivers/gpu/mali400/r3p2/mali/platform/pegasus-m400/exynos4_pmm.c')
| -rw-r--r-- | drivers/gpu/mali400/r3p2/mali/platform/pegasus-m400/exynos4_pmm.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/mali400/r3p2/mali/platform/pegasus-m400/exynos4_pmm.c b/drivers/gpu/mali400/r3p2/mali/platform/pegasus-m400/exynos4_pmm.c index 346ad7f..ce74d80 100644 --- a/drivers/gpu/mali400/r3p2/mali/platform/pegasus-m400/exynos4_pmm.c +++ b/drivers/gpu/mali400/r3p2/mali/platform/pegasus-m400/exynos4_pmm.c @@ -106,8 +106,8 @@ mali_dvfs_table mali_dvfs[MALI_DVFS_STEPS]={ #define ASV_LEVEL 12 /* ASV0, 1, 11 is reserved */ #define ASV_LEVEL_PRIME 13 /* ASV0, 1, 12 is reserved */ #define ASV_LEVEL_PD 13 -#define ASV_LEVEL_4210_12 8 -#define ASV_LEVEL_4210_14 5 +#define ASV_LEVEL_4210_12» 8 +#define ASV_LEVEL_4210_14» 5 #if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412) static unsigned int asv_3d_volt_9_table_1ghz_type[MALI_DVFS_STEPS-1][ASV_LEVEL] = { @@ -163,7 +163,6 @@ static unsigned int asv_3d_volt_4212_9_table[MALI_DVFS_STEPS][ASV_LEVEL_PD] = { #endif #endif }; - #else static unsigned int asv_3d_volt_4210_12_table[MALI_DVFS_STEPS][ASV_LEVEL_4210_12] = { @@ -481,6 +480,9 @@ void mali_clk_set_rate(unsigned int clk, unsigned int mhz) if (bis_vpll) { + /* in Pega-prime, vpll_src_clock means ext_xtal_clock!! */ + clk_set_parent(sclk_vpll_clock, vpll_src_clock); + clk_set_rate(fout_vpll_clock, (unsigned int)clk * GPU_MHZ); clk_set_parent(vpll_src_clock, ext_xtal_clock); clk_set_parent(sclk_vpll_clock, fout_vpll_clock); @@ -1258,7 +1260,7 @@ int mali_dvfs_bottom_lock_pop(void) if (prev_status <= 0) { MALI_PRINT(("gpu bottom lock status is not valid for pop\n")); return -1; - } else if (prev_status == 1) { + } else if (prev_status >= 1) { bottom_lock_step = 0; MALI_PRINT(("gpu bottom lock release\n")); } |